參數(shù)資料
型號: KAC-1310
廠商: Electronic Theatre Controls, Inc.
英文描述: 1280 (H) x 1024 (V) SXGA CMOS Image Sensor
中文描述: 1280(高)x 1024(五)SXGA CMOS圖像傳感器
文件頁數(shù): 64/76頁
文件大?。?/td> 759K
代理商: KAC-1310
IMAGE SENSOR SOLUTIONS
64
IMAGE SENSOR SOLUTIONS
K A C - 1 3 1 0 R e v 4 w w w . k o d a k . c o m / g o / i m a g e r s 5 8 5 - 7 2 2 - 4 3 8 5 E m a i l : i m a g e r s @ k o d a k . c o m
SOF and VCLK Delay Registers (54
h
and 55
h
)
This adjust can be used to vary the sync positions
(rising and falling edges) relative to valid pixel
data. In this way an acquisition system that uses
the sync pulses for display can be shifted to add or
avoid image borders. Adjusting the position or
length of the SOF or VCLK sync does NOT alter
the Frame Rate, the sync signal is simply shifted
and overlaps the valid line and pixel data. Moving
the rising edge of the SOF will also move the
rising edge of the VCLK. This is so that the VCLK
sync does not occur before the SOF pulse. The
delay adjust is in cycles, it takes two
programmed counts to delay the rising edge by
one image pixel. These delays are measured
from the change of the row address, which is not
directly observable except to set the delay to 0.
Address
54
h
SOF Delay
Default
4C
h
7 (msb)
6
5
4
3
2
1
0 (lsb)
sofd[7]
sofd[6]
sofd[5]
sofd[4]
sofd[3]
sofd[2]
sofd[1]
sofd[0]
Bit
Number
Function
Description
Reset
State
7 - 0
SOF Delay Delay = sofd
d
* 0.5 MCLK's
01001100
b
Table 44: SOF Delay Register (54
h
)
Address
55
h
VCLK Delay
Default
02
h
7 (msb)
6
5
4
3
2
1
0 (lsb)
vckd[7]
vckd[6]
vckd[5]
vckd[4]
vckd[3]
vckd[2]
vckd[1]
vckd[0]
Bit
Number
Function
Description
Reset
State
7 - 0
VCLK Delay Delay = vckd
d
* 0.5 MCLK's
00000010
b
Table 45: VCLK Delay Register (55
h
)
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