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| 型號(hào)： | KAC-1310 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1280 (H) x 1024 (V) SXGA CMOS Image Sensor |
| 中文描述： | 1280（高）x 1024（五）SXGA CMOS圖像傳感器 |
| 文件頁數(shù)： | 55/76頁 |
| 文件大小： | 759K |
| 代理商： | KAC-1310 |
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IMAGE SENSOR SOLUTIONS
55
IMAGE SENSOR SOLUTIONS
K A C - 1 3 1 0 R e v 4 w w w . k o d a k . c o m / g o / i m a g e r s 5 8 5 - 7 2 2 - 4 3 8 5 E m a i l : i m a g e r s @ k o d a k . c o m
Capture Mode Control (40
h
)
The Capture Mode Control Register defines how
the data is captured and how the data is to be
provided at the output. Setting the
cms
bit will
stop the current CFRS output data stream at the
end of the current frame and place the imager in
Single Frame Capture Mode (SFRS). While the
cms
bit is set (SFRS), the output of frames can be
paused with the TRIGGER input pin. When the
TRIGGER pin is low (V
SS
) the output of frames is
suspended. When the TRIGGER pin is high (V
DD
)
frames are continuous. The default for
cms
is 0
(CFRS). In CFRS the frames are continuously
output and the TRIGGER pin is ignored. The
Frame Rate is slightly reduced when the
cms
is
set (SFRS) because care is taken in the startup
such that the first frame output is valid. This
causes a slight delay at the start of each frame.
See
Figure 22
on
page
32
for a timing diagram for
SFRS mode. With the
cms
low(=0), the Frame
Rate is faster, but the first frame will be invalid
(wrong integration time).
Address
40
h
When the
hm
bit is set, the HCLK sync is high
whenever valid WOI pixel data is being clocked
out and low during the other blanking intervals.
The HCLK does NOT toggle at the MCLK rate
when the
hm
bit is set. When
hm
is set the HCLK
will go high once at the beginning of the valid pixel
data and remain high until the last WOI pixel has
been clocked out. When the
hm
bit is set the
he
bit is ignored. The
sp
bit is used to define whether
SOF is active high or low. SOF is active high by
default. The
ve
bit is used to determine whether
VCLK is output at the beginning of the virtual
frame rows or only for the WOI rows. The
ve
bit
defaults to VCLK on WOI rows only. The
vp
bit is
used to define whether VCLK is active high(the
default) or active low. The
he
bit is used to
determine whether HCLK is output continuously
(needed for some frame grabbers) or only for
pixels within the WOI (default). The
hp
bit is used
to define whether HCLK is active high (default) or
low.
Capture Mode Control
Default
2A
h
7 (msb)
6
5
4
3
2
1
0 (lsb)
FUO
cms
sp
ve
vp
he
hp
hm
Bit
Number
Function
Description
Reset
State
7
FUO
Factory Use Only
0
b
6
RSCM
Mode
0
b
= Continuous Frame Rolling Shutter (CFRS)
1
b
= Single Frame Rolling Shutter (SFRS)
0
b
5
SOF
Phase
0
b
= SOF sync active low
1
b
= SOF sync active high
1
b
4
VCLK
Enable
0
b
= VCLK Sync on WOI rows only
1
b
= VCLK Sync on WOI and Virtual Rows
0
b
3
VCLK
Phase
0
b
= Active low
1
b
= Active high
1
b
2
HCLK
Enable
0
b
= Pixel sync on WOI pixels only
1
b
= Continuous pixel sync
0
b
1
HCLK
Phase
0
b
= Active low
1
b
= Active high
1
b
0
HCLK
Mode
0
b
= Toggles - Toggles at MCLK rates defined by (he) bit
1
b
= Continuous - Pixel Valid Envelope
0
b
Table 27: Capture Mode Register (40
h
)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KAC-15 | 功能描述:保險(xiǎn)絲 600V 15A Semiconductor RoHS:否 制造商:Littelfuse 產(chǎn)品:Surface Mount Fuses 電流額定值:0.5 A 電壓額定值:600 V 保險(xiǎn)絲類型:Fast Acting 保險(xiǎn)絲大小/組:Nano 尺寸:12.1 mm L x 4.5 mm W 安裝風(fēng)格: 端接類型:SMD/SMT 系列:485 |
| KAC-150 | 功能描述:保險(xiǎn)絲 600V 150A Semiconductor RoHS:否 制造商:Littelfuse 產(chǎn)品:Surface Mount Fuses 電流額定值:0.5 A 電壓額定值:600 V 保險(xiǎn)絲類型:Fast Acting 保險(xiǎn)絲大小/組:Nano 尺寸:12.1 mm L x 4.5 mm W 安裝風(fēng)格: 端接類型:SMD/SMT 系列:485 |
| KAC-17.5 | 制造商:COOPER 制造商全稱:Cooper Bussmann, Inc. 功能描述:High Speed Fuses |
| KAC-17-1/2 | 功能描述:保險(xiǎn)絲 600V 17.5A Semiconductor RoHS:否 制造商:Littelfuse 產(chǎn)品:Surface Mount Fuses 電流額定值:0.5 A 電壓額定值:600 V 保險(xiǎn)絲類型:Fast Acting 保險(xiǎn)絲大小/組:Nano 尺寸:12.1 mm L x 4.5 mm W 安裝風(fēng)格: 端接類型:SMD/SMT 系列:485 |
| KAC-17-1-2 | 制造商:Cooper Bussmann 功能描述:FUSE 17.5A 600V 2PIN - Bulk |
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