參數(shù)資料
型號(hào): KAC-1310
廠商: Electronic Theatre Controls, Inc.
英文描述: 1280 (H) x 1024 (V) SXGA CMOS Image Sensor
中文描述: 1280(高)x 1024(五)SXGA CMOS圖像傳感器
文件頁數(shù): 51/76頁
文件大小: 759K
代理商: KAC-1310
IMAGE SENSOR SOLUTIONS
51
IMAGE SENSOR SOLUTIONS
K A C - 1 3 1 0 R e v 4 w w w . k o d a k . c o m / g o / i m a g e r s 5 8 5 - 7 2 2 - 4 3 8 5 E m a i l : i m a g e r s @ k o d a k . c o m
Column DOVA DC Register (20
h
)
Offset adjustments for the KAC-1310 are done in
separate sections of the ASP to facilitate FPN
removal and final image black level set. The
primary purpose of the Column DOVA DC
Register is to compensate for pre-gain offset. If
this register is set to zero the user may find that
the dark level of some chips may move with
different programmed gain values. In addition the
white balance gain stage can result in different
effective dark levels for different colors. These
effects MAY cause distortion with certain post
image signal processing. In these cases the
Column DOVA DC Register can be programmed
such that the dark pixel level is independent of
programmed gain values. The simplest method
for setting this register is to place the imager in the
dark and record the mean value for the dark
pixels. Then increase the global gain register
(10
h
) to the maximum gain to be used in the
application. Adjust register 20
h
until the dark level
Address
has returned to the level previously recorded with
unity gain. This process can be repeated again for
greater accuracy since the dark level at unity gain
will now have shifted slightly. For many
applications, this register can be left in its default
state of 00
h
. If during the calibration of this register
the value of any pixels are observed to be clipping
at zero counts, it is then necessary to temporarily
increase the ADC DOVA (reg 23
h
) to avoid
clipping. Register 20
h
should not be used to adjust
the code value of the dark level for the ADC, this
should always be done with the ADC DOVA (reg
23
h
)
The Column DOVA stage is also used to correct
for patterned column noise. This is done pre-gain.
The column pattern correction offsets are defined
in Reg 80
h
BF
h
, see
Table 52
on
page
70
. The
Column DOVA stage has only six bits of
programmability. Registers 20
h
is added to the
value in 80
h
BF
h
for that column. The final sum
is clipped to ±32
d
.
20
h
Column DOVA DC
Default
00
h
7 (msb)
6
5
4
3
2
1
0 (lsb)
x
x
cdd[5]
cdd[4]
cdd[3]
cdd[2]
cdd[1]
cdd[0]
Bit
Number
Function Description
Reset
State
7 - 6
Unused
Unused
xx
b
5
Sign
0
b
= Positive Offset
1
b
= Negative Offset
0
b
4 - 0
Column
DC Offset
Offset = 2.6 * cdd
d
(64 steps @ 2.6
mV/step)
00000
b
Table 23: Column DOVA DC Offset (20
h
)
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