參數(shù)資料
型號: K4E640411D-TC500
元件分類: DRAM
英文描述: 16M X 4 EDO DRAM, 50 ns, PDSO32
封裝: 0.400 INCH, PLASTIC, TSOP2-32
文件頁數(shù): 19/21頁
文件大小: 407K
代理商: K4E640411D-TC500
CMOS DRAM
K4E660411D, K4E640411D
TEST MODE CYCLE
Parameter
Symbol
-50
-60
Units
Note
Min
Max
Min
Max
Random read or write cycle time
tRC
89
109
ns
Read-modify-write cycle time
tRWC
121
145
ns
Access time from RAS
tRAC
55
65
ns
3,4,10,12
Access time from CAS
tCAC
18
20
ns
3,4,5,12
Access time from column address
tAA
30
35
ns
3,10,12
RAS pulse width
tRAS
55
10K
65
10K
ns
CAS pulse width
tCAS
13
10K
15
10K
ns
RAS hold time
tRSH
18
20
ns
CAS hold time
tCSH
43
50
ns
Column Address to RAS lead time
tRAL
30
35
ns
CAS to W delay time
tCWD
35
39
ns
7
RAS to W delay time
tRWD
72
84
ns
7
Column Address to W delay time
tAWD
47
54
ns
7
Hyper Page cycle time
tHPC
25
30
ns
13
Hyper Page read-modify-write cycle time
tHPRWC
53
61
ns
13
RAS pulse width (Hyper page cycle)
tRASP
55
200K
65
200K
ns
Access time from CAS precharge
tCPA
33
40
ns
3
OE access time
tOEA
18
20
ns
OE to data delay
tOED
18
20
ns
OE command hold time
tOEH
18
20
ns
( Note 11 )
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