參數(shù)資料
型號: ISPLSI3448
廠商: Lattice Semiconductor Corporation
英文描述: In-System Programmable High Density PLD
中文描述: 在系統(tǒng)可編程高密度可編程邏輯器件
文件頁數(shù): 6/14頁
文件大?。?/td> 144K
代理商: ISPLSI3448
Specifications
ispLSI 3448
6
External Switching Characteristics
1, 2, 3
Over Recommended Operating Conditions
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
toeen
t
toedis
t
wh
t
wl
t
su3
t
h3
UNITS
-90
MIN.
90.0
TEST
COND.
1. Unless noted otherwise, all parameters use 20 PTXOR path and ORP.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4.
f
max (Toggle) may be less than 1/(
t
wh +
t
wl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions section.
Table 2-0030/3320
1
5
3
1
( )
-70
MIN.
70.0
MAX.
12.0
15.0
MAX.
15.0
18.0
DESCRIPTION
#
2
PARAMETER
A
A
A
1 Data Propagation Delay, 4PT Bypass, ORP Bypass
2 Data Propagation Delay
3 Clock Frequency with Internal Feedback
ns
ns
MHz
A
4 Clock Frequency with External Feedback
5 Clock Frequency, Maximum Toggle
6 GLB Reg. Setup Time before Clock, 4 PT Bypass
7 GLB Reg. Clock to Output Delay, ORP Bypass
8 GLB Reg. Hold Time after Clock, 4 PT Bypass
MHz
MHz
ns
ns
ns
4
7.5
A
B
C
B
C
B
C
9 GLB Reg. Setup Time before Clock
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
18 Test OE Output Enable
19 Test OE Output Disable
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20 Ext. Synchronous Clock Pulse Duration, High
21 Ext. Synchronous Clock Pulse Duration, Low
22 I/O Reg Setup Time before Ext. Synchronous Clock (Y3, Y4)
23 I/O Reg Hold Time after Ext. Sync Clock (Y3, Y4)
5.0
5.0
4.5
0.0
ns
ns
ns
ns
62.5
100
7.0
0.0
8.5
0.0
9.0
8.0
14.0
25.0
25.0
10.0
10.0
13.0
13.0
50.0
83.0
9.0
0.0
11.0
0.0
12.0
6.0
6.0
5.0
0.0
9.0
10.0
15.0
30.0
30.0
12.0
12.0
15.0
15.0
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