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參數(shù)資料
| 型號(hào)： | ISPLSI3448 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable High Density PLD |
| 中文描述： | 在系統(tǒng)可編程高密度可編程邏輯器件 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大小： | 144K |
| 代理商： | ISPLSI3448 |
Specifications
ispLSI 3448
3
All local logic block outputs are brought back into the
GRP so they can be connected to the inputs of any other
logic block on the device. The device also has 224 I/O
cells, each of which is directly connected to an I/O ball.
Each I/O cell can be individually programmed to be a
combinatorial input, a registered input, a latched input, an
output or a bidirectional I/O with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
The 224 I/O cells are grouped into 14 sets of 16 bits. Each
of these I/O groups is associated with a logic Megablock
through the use of the ORP. Each Megablock is able to
provide one Product Term Output Enable (PTOE) signal
which is globally distributed to all I/O cells. That PTOE
signal can be generated within any GLB in the Megablock.
Each I/O cell can select one of 16 available OEs (two
Global OEs and 14 PTOEs).
Four Twin GLBs, 16 I/O cells and one ORP are con-
nected together to make a logic Megablock. The
Megablock is defined by the resources that it shares. The
outputs of the four Twin GLBs are connected to a set of
16 I/O cells by the ORP. The ispLSI 3448 device
contains 14 of these Megablocks.
The GRP has as its inputs the outputs from all of the Twin
GLBs and all of the inputs from the bidirectional I/O cells.
All of these signals are made available to the inputs of the
Twin GLBs. Delays through the GRP have been equal-
ized to minimize timing skew and logic glitching.
Clocks in the ispLSI 3448 device are provided through
five dedicated signals. Three clocks are provided for the
Twin GLBs and the remaining two clocks are provided for
the I/O cells.
The table below lists key attributes of the device along
with the number of resources available.
An additional feature of the ispLSI 3448 is the Boundary
Scan capability, which is composed of cells connected
between the on-chip system logic and the device’s inputs
and outputs. All I/O have associated boundary scan
registers, with 3-state I/O using three boundary scan
registers and inputs using one.
The ispLSI 3448 supports all IEEE 1149.1 mandatory
instructions, which include BYPASS, EXTEST and
SAMPLE.
Key Attributes of the ispLSI 3448
Attribute
Twin GLBs
Registers
I/O
Global Clocks
Global OE
Test OE
Quantity
56
672
224
5
2
1
Table 1-0003/3448
Description (continued)
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| ISPLSI5128VE | In-System Programmable 3.3V SuperWIDE High Density PLD |
| ISPLSI5128VE-80LT128I | In-System Programmable 3.3V SuperWIDE High Density PLD |
| ISPLSI5128VE-100LT128 | In-System Programmable 3.3V SuperWIDE High Density PLD |
| ISPLSI5128VE-100LT128I | In-System Programmable 3.3V SuperWIDE High Density PLD |
| ISPLSI5128VE-125LT128 | In-System Programmable 3.3V SuperWIDE High Density PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI-3448-70LB432 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
| ISPLSI-3448-90LB432 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
| ISPLSI5128VE-100LT128 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5128VE-100LT128I | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5128VE-125LT128 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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