參數(shù)資料
型號(hào): ISP1183
廠(chǎng)商: NXP Semiconductors N.V.
英文描述: Low-power Universal Serial Bus interface device with DMA
中文描述: 低功耗通用串行總線(xiàn)與DMA接口設(shè)備
文件頁(yè)數(shù): 9/62頁(yè)
文件大?。?/td> 295K
代理商: ISP1183
Philips Semiconductors
ISP1183
Low-power USB interface device with DMA
Product data
Rev. 01 — 24 February 2004
9 of 62
9397 750 11804
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.5 Bit clock recovery
The bit clock recovery circuit recovers the clock from the incoming USB data stream
using a 4 x oversampling principle. It can track jitter and frequency drift as specified
by the USB Specification Rev. 2.0
8.6 Voltage regulator
A 5 V-to-3.3 V voltage regulator is integrated on-chip to supply the analog transceiver
and internal logic. This voltage is available at pin V
REG(3V3)
to supply an external
1.5 k
pull-up resistor on pin DP. Alternatively, the ISP1183 provides SoftConnect
technology through an integrated 1.5 k
pull-up resistor (see
Section 8.4
).
8.7 PLL clock multiplier
A 6 MHz-to-48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip.
This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No
external components are required for the operation of the PLL.
8.8 PIO and DMA interfaces
A generic Parallel I/O (PIO) interface is defined for speed and ease-of-use. It also
allows direct interfacing to most microcontrollers. To a microcontroller, the ISP1183
appears as a memory device with an 8-bit data bus and a 1-bit address bus. The
ISP1183 supports nonmultiplexed address and data buses.
The ISP1183 can also be configured as a Direct Memory Access (DMA) slave device
to allow more efficient data transfer. One of the 14 endpoint FIFOs may directly
transfer data to or from the local shared memory. The DMA interface can be
independently configured from the PIO interface.
It can be directly interfaced to microprocessors or microcontrollers with I/O voltage
range as low as 1.65 V.
8.9 V
BUS
indicator
The ISP1183 indicates the availability of V
BUS
using the V
BUS
pin. When V
BUS
is
available (at pin V
BUS
), pin VBUSDET_N will output LOW. When V
BUS
is not available
(at pin V
BUS
), pin VBUSDET_N will output HIGH. Pin VBUSDET_N will change from
HIGH-to-LOW level in approximately 2.5 ms to 3.5 ms. See
Section 19
.
8.10 Operation modes
The ISP1183 can be operated in several operation modes as given in
Table 3
.
Table 3:
Pin name
ISP1183 operation modes
Plug-out
state
0 V
1.8 V
X
X
H
Dead state
Reset state
Plug-in state
Normal state
V
BUS
V
DD(I/O)
WAKEUP
RESET_N
INT_N
X
0 V
X
X
L
[1]
5 V
1.8 V
L
L
H
5 V
1.8 V
L
H
H
5 V
1.8 V
L
H
-
[2]
相關(guān)PDF資料
PDF描述
ISP1183BS Low-power Universal Serial Bus interface device with DMA
ISP1301 Universal Serial Bus On-The-Go transceiver
ISP1301BS Universal Serial Bus On-The-Go transceiver
ISP1362 Single-chip Universal Serial Bus On-The-Go controller
ISP1362BD Single-chip Universal Serial Bus On-The-Go controller
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