參數(shù)資料
型號: ISP1183
廠商: NXP Semiconductors N.V.
英文描述: Low-power Universal Serial Bus interface device with DMA
中文描述: 低功耗通用串行總線與DMA接口設備
文件頁數(shù): 27/62頁
文件大小: 295K
代理商: ISP1183
Philips Semiconductors
ISP1183
Low-power USB interface device with DMA
Product data
Rev. 01 — 24 February 2004
27 of 62
9397 750 11804
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
[2]
[3]
Validating an OUT endpoint buffer causes unpredictable behavior of the ISP1183.
Clearing an IN endpoint buffer causes unpredictable behavior of the ISP1183.
Reads a copy of the Status register: executing this command does not clear any status bits or interrupt bits.
13.1 Initialization commands
Initialization commands are used during the enumeration process of the USB
network. These commands are used to configure and enable the embedded
endpoints. They also set the USB assigned address of the ISP1183 and perform
device reset.
13.1.1
Endpoint Configuration register (R/W: 30H–3FH/20H–2FH)
This command accesses the Endpoint Configuration register (ECR) of the target
endpoint. It defines the endpoint type (isochronous or bulk/interrupt), direction
(OUT/IN), FIFO size and buffering scheme. It also enables the endpoint FIFO. The
register bit allocation is shown in
Table 14
. A bus reset will disable all endpoints.
The allocation of FIFO memory takes place only after
all
16 endpoints have been
configured in sequence (from endpoint 0 OUT to endpoint 14). Although the control
endpoints have fixed configurations, they must be included in the initialization
sequence and configured with their default values (see
Table 4
). Automatic FIFO
allocation starts when endpoint 14 is configured.
Remark:
If any change is made to an endpoint configuration that affects the allocated
memory (size, enable/disable), the FIFO memory contents of
all
endpoints become
invalid. Therefore, all valid data must be removed from enabled endpoints before
changing the configuration.
Code (hex): 20 to 2F —
write (control OUT, control IN, endpoints 1 to 14)
DMA commands
Write or read DMA Function and
Scratch register
Write or read DMA
Configuration
Write or read DMA Counter
General commands
Read Control OUT Error Code
DMA Function and
Scratch register
DMA Configuration
register
DMA Counter register
B2/B3
write or read 2 bytes
Section 13.3.1 on page 36
F0/F1
write or read 2 bytes
Section 13.3.2 on page 37
F2/F3
write or read 2 bytes
Section 13.3.3 on page 38
Error Code register
endpoint 0 OUT
Error Code register
endpoint 0 IN
Error Code register
endpoints 1 to 14
all registers with write
access
Frame Number register
Chip ID register
Interrupt register
A0
read 1 byte
Section 13.4.1 on page 38
Read Control IN Error Code
A1
read 1 byte
Read Endpoint n Error Code
(n = 1 to 14)
Unlock Device
A2 to AF
read 1 byte
B0
write 2 bytes
Section 13.4.2 on page 39
Read Frame Number
Read Chip ID
Read Interrupt register
B4
B5
C0
read 1 or 2 bytes
read 2 bytes
read 4 bytes
Section 13.4.3 on page 40
Section 13.4.4 on page 41
Section 13.4.5 on page 41
Table 13:
Name
Command and register summary
…continued
Destination
Code
(hex)
Transaction
Reference
相關PDF資料
PDF描述
ISP1183BS Low-power Universal Serial Bus interface device with DMA
ISP1301 Universal Serial Bus On-The-Go transceiver
ISP1301BS Universal Serial Bus On-The-Go transceiver
ISP1362 Single-chip Universal Serial Bus On-The-Go controller
ISP1362BD Single-chip Universal Serial Bus On-The-Go controller
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