參數(shù)資料
型號: ISP1183
廠商: NXP Semiconductors N.V.
英文描述: Low-power Universal Serial Bus interface device with DMA
中文描述: 低功耗通用串行總線與DMA接口設備
文件頁數(shù): 49/62頁
文件大?。?/td> 295K
代理商: ISP1183
Philips Semiconductors
ISP1183
Low-power USB interface device with DMA
Product data
Rev. 01 — 24 February 2004
49 of 62
9397 750 11804
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
18.2 Access cycle timing
(1) If required, CS_N can be kept permanently asserted. There is no need to deassert and assert in between the read and
write cycles.
Fig 13. Parallel interface read timing.
004aaa256
A0
tRHAX
tAVRL
tRLRH
tRLDV
tRHRL
(1)
DATA
RD_N
CS_N
tRHSH
tRHDZ
tSLRL
(1) If required, CS_N can be kept permanently asserted. There is no need to deassert and assert in between the read and
write cycles.
Fig 14. Parallel interface write timing.
004aaa257
CS_N
A0
DATA
WR_N
tWHAX
tAVWL
tWHDZ
tDVWH
tWLWH
tWHSH
tWHWL
(1)
tSLWL
Table 56:
V
BUS
= V
REG(3V3)
= 2.7 V to 3.9 V; V
DD(I/O)
= 1.8 V
Symbol
Parameter
Write command + write data (see
Figure 15
and
Figure 16
)
T
cy(WC-WD)
cycle time for write command, then write data
T
cy(WD-WD)
cycle time for write data
T
cy(WD-WC)
cycle time for write data, then write command
Dynamic characteristics: access cycle timing
Conditions
Min
Max
Unit
C
L
= 30 pF
[1]
100
90
90
-
-
-
ns
ns
ns
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