參數(shù)資料
型號: ISP1183
廠商: NXP Semiconductors N.V.
英文描述: Low-power Universal Serial Bus interface device with DMA
中文描述: 低功耗通用串行總線與DMA接口設(shè)備
文件頁數(shù): 14/62頁
文件大?。?/td> 295K
代理商: ISP1183
Philips Semiconductors
ISP1183
Low-power USB interface device with DMA
Product data
Rev. 01 — 24 February 2004
14 of 62
9397 750 11804
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10. Endpoint description
Each USB device is logically composed of several independent endpoints. An
endpoint acts as a terminus of a communication flow between the host and the
device. At design time, each endpoint is assigned a unique number (endpoint
identifier, see
Table 4
). The combination of the device address (given by the host
during enumeration), the endpoint number, and the transfer direction allows each
endpoint to be uniquely referenced.
The ISP1183 has 16 endpoints: endpoint 0 (control IN and OUT) plus 14 configurable
endpoints, which can be individually defined as interrupt, bulk or isochronous—IN or
OUT. Each enabled endpoint has an associated FIFO, which can be accessed either
using the parallel I/O interface or DMA.
10.1 Endpoint access
Table 4
lists the endpoint access modes and programmability. All endpoints support
I/O mode access. Endpoints 1 to 14 also support DMA access. FIFO DMA access is
selected and enabled through bits EPDIX[3:0] and DMAEN of the DMA Configuration
register. A detailed description of the DMA operation is given in
Section 11
.
[1]
[2]
The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes.
IN: input for the USB host (ISP1183 transmits); OUT: output from the USB host (ISP1183 receives). The data flow direction is
determined by bit EPDIR in the Endpoint Configuration register.
10.2 Endpoint FIFO size
The FIFO size determines the maximum packet size that the hardware can support
for a given endpoint. Only enabled endpoints are allocated space in the shared FIFO
storage, disabled endpoints have zero bytes.
Table 5
lists programmable FIFO sizes.
The following bits in the Endpoint Configuration register (ECR) affect FIFO allocation:
Endpoint enable bit (FIFOEN)
Size bits of an enabled endpoint (FFOSZ[3:0])
Isochronous bit of an enabled endpoint (FFOISO).
Remark:
Register changes that affect the allocation of the shared FIFO storage
among endpoints must
not
be made while valid data is present in any FIFO of the
enabled endpoints. Such changes will render
all
FIFO contents
undefined
.
Table 4:
Endpoint
identifier
0
0
1 to 14
Endpoint access and programmability
FIFO size (bytes)
[1]
Double buffering
I/O mode
access
yes
yes
supported
DMA mode
access
no
no
supported
Endpoint type
64 (fixed)
64 (fixed)
programmable
no
no
supported
control OUT
[2]
control IN
[2]
programmable
相關(guān)PDF資料
PDF描述
ISP1183BS Low-power Universal Serial Bus interface device with DMA
ISP1301 Universal Serial Bus On-The-Go transceiver
ISP1301BS Universal Serial Bus On-The-Go transceiver
ISP1362 Single-chip Universal Serial Bus On-The-Go controller
ISP1362BD Single-chip Universal Serial Bus On-The-Go controller
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