參數(shù)資料
型號: ISP1181DGG
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: INDUCTOR 4.7NH +-.3NH 0402 SMD
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PDSO48
封裝: 6.10 MM, PLASTIC, TSSOP-48
文件頁數(shù): 50/69頁
文件大小: 1655K
代理商: ISP1181DGG
Philips Semiconductors
ISP1181
Full-speed USB interface
Objective specification
Rev. 01 — 13 March 2000
50 of 69
9397 750 06896
Philips Electronics N.V. 2000. All rights reserved.
19.2 Parallel I/O timing
[1]
[2]
[3]
Measured from CS going HIGH to CS and RD both going LOW.
Measured from CS going HIGH to CS and WR both going LOW.
Commands Acknowledge Setup, Clear Buffer, Validate Buffer and Write Endpoint Configuration require 180 ns to complete.
Table 59: Dynamic characteristics: parallel interface timing
Symbol
Parameter
Conditions
8-bit bus
16-bit bus
Unit
Min
Max
Min
Max
Read timing (see
Figure 20
and
Figure 21
)
t
RHAX
address hold after RD HIGH
t
AVRL
address setup before RD LOW
t
SHDZ
data outputs high-impedance
after CS HIGH
t
RLRH
RD pulse width
t
RLDV
data valid after RD LOW
t
SHRL1
read interval after CS HIGH
[1]
t
SHRL2
read interval after CS HIGH
[1]
t
YHRH
output READY HIGH before
RD HIGH
t
RC
read cycle duration
Write timing (see
Figure 22
and
Figure 23
)
t
WHAX
address hold after WR HIGH
t
AVWL
address setup before WR LOW
t
SHWL1
write interval after CS HIGH
[2]
t
SHWL2
write interval after CS HIGH
[2]
t
WLWH
WR pulse width
t
WHSH
chip deselect after WR HIGH
t
DVWH
data setup before WR HIGH
t
WHDZ
data hold after WR HIGH
t
WC
write cycle duration
ALE timing (see
Figure 24
)
t
LH
ALE pulse width
t
AVLL
address setup before ALE
LOW
t
LLAX
address hold after ALE LOW
3
0
-
-
-
3
3
0
-
-
-
3
ns
ns
ns
25
-
22
90
0
-
22
-
-
-
25
-
22
180
0
-
22
-
-
-
ns
ns
ns
ns
ns
READY pulsing
READY = HIGH
-
90
-
180
ns
3
0
22
90/180
[3]
22
0
5
3
-
-
-
-
-
-
-
-
-
90/180
[3]
3
0
22
180
22
0
5
3
-
-
-
-
-
-
-
-
-
180
ns
ns
ns
ns
ns
ns
ns
ns
ns
READY pulsing
READY = HIGH
20
10
-
-
20
10
-
-
ns
ns
reading
writing
0
0
10
-
0
0
10
-
ns
ns
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