參數(shù)資料
型號: ISP1181DGG
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: INDUCTOR 4.7NH +-.3NH 0402 SMD
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PDSO48
封裝: 6.10 MM, PLASTIC, TSSOP-48
文件頁數(shù): 31/69頁
文件大小: 1655K
代理商: ISP1181DGG
Philips Semiconductors
ISP1181
Full-speed USB interface
Objective specification
Rev. 01 — 13 March 2000
31 of 69
9397 750 06896
Philips Electronics N.V. 2000. All rights reserved.
12.1.7
Write/Read DMA Counter
This command accesses the DMA Counter Register, which consists of 2 bytes. The
bit allocation is given in
Table 28
. Writing to the register sets the number of bytes for a
DMA transfer. Reading the register returns the number of remaining bytes in the
current transfer. A bus reset will not change the programmed bit values.
The internal DMA counter is automatically reloaded from the DMA Counter Register,
when DMA is re-enabled (DMAEN = 1) or upon completion of a DMA transfer, when
auto-restart is enabled (AUTOLD = 1). See
Section 12.1.6
for more details.
Code (Hex): F2/F3 —
write/read DMA Counter Register
Transaction —
write/read 2 bytes
3
DMAEN
Writing a logic 1 enables DMA transfer, a logic 0 forces the end
of an ongoing DMA transfer and generates an EOT interrupt.
Reading this bit indicates whether DMA is enabled (0 = DMA
stopped, 1 = DMA enabled). This bit is cleared by a bus reset.
A logic 1 enables automatic restarting of DMA transfers. This bit
is cleared by a bus reset.
Selects the DMA burst length:
00 —
single-cycle mode (1 byte)
01 —
burst mode (4 bytes)
10 —
burst mode (8 bytes)
11 —
burst mode (16 bytes).
Bus reset value: unchanged.
2
AUTOLD
1 to 0
BURSTL[1:0]
Table 27: DMA Configuration Register: bit description
Bit
Symbol
Description
Table 28: DMA Counter Register: bit allocation
Bit
15
Symbol
Reset
0
Access
R/W
Bit
7
Symbol
Reset
0
Access
R/W
14
13
12
DMACRH[7:0]
0
R/W
4
DMACRL[7:0]
0
R/W
11
10
9
8
0
0
0
0
0
0
R/W
6
R/W
5
R/W
3
R/W
2
R/W
1
R/W
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Table 29: DMA Counter Register: bit description
Bit
Symbol
15 to 8
DMACRH[7:0]
7 to 0
DMACRL[7:0]
Description
DMA Counter Register (high byte)
DMA Counter Register (low byte)
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