參數(shù)資料
型號: ISP1181A
廠商: NXP Semiconductors N.V.
英文描述: Full-speed Universal Serial Bus peripheral controller
中文描述: 全速通用串行總線外設控制器
文件頁數(shù): 7/70頁
文件大?。?/td> 341K
代理商: ISP1181A
Philips Semiconductors
ISP1181A
Full-speed USB peripheral controller
Product data
Rev. 05 — 08 December 2004
7 of 70
9397 750 13959
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
DATA5
31
26
I/O
bit 5 of D[15:0]; bidirectional data line
(slew-rate controlled output, 4 mA)
bit 4 of D[15:0]; bidirectional data line
(slew-rate controlled output, 4 mA)
bit 3 of D[15:0]; bidirectional data line
(slew-rate controlled output, 4 mA)
bit 2 of D[15:0]; bidirectional data line
(slew-rate controlled output, 4 mA)
bit 1 of D[15:0]; bidirectional data line
(slew-rate controlled output, 4 mA)
ground supply
supply voltage (3.0 V to 3.6 V); leave this
pin unconnected when using V
CC
= 5.0 V
multiplexed bidirectional address and data
line; represents address A0 or bit 0 of
D[15:0] in conjunction with input ALE;
level-sensitive input or slew-rate controlled
output (4 mA)
Address phase
: a HIGH-to-LOW transition
on input ALE latches the level on this pin as
address A0 (1 = command, 0 = data)
Data phase
: during reading this pin outputs
bit D[0]; during writing the level on this pin is
latched as bit D[0]
address input; selects command (A0 = 1) or
data (A0 = 0); in a multiplexed address/data
bus configuration this pin is not used and
must be tied LOW (connect to GND)
read strobe input
write strobe input
address latch enable input; a HIGH-to-LOW
transition latches the level on pin AD0 as
address information in a multiplexed
address/data bus configuration; must be
tied LOW (connect to GND) for a separate
address/data bus configuration
chip select input
reset input (Schmitt trigger); a LOW level
produces an asynchronous reset; connect
to V
CC
for power-on reset (internal POR
circuit)
programmable clock output (2 mA)
DATA4
32
27
I/O
DATA3
33
28
I/O
DATA2
34
29
I/O
DATA1
35
30
I/O
GND
V
CC(3.3)
36
37
31
32
-
-
AD0
38
33
I/O
A0
39
34
I
RD
WR
ALE
40
41
42
35
36
37
I
I
I
CS
RESET
43
44
38
39
I
I
CLKOUT
45
40
O
Table 2:
Symbol
[1]
Pin description
…continued
Pin
TSSOP48
Type
Description
HVQFN48
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