參數(shù)資料
型號: ISP1181A
廠商: NXP Semiconductors N.V.
英文描述: Full-speed Universal Serial Bus peripheral controller
中文描述: 全速通用串行總線外設(shè)控制器
文件頁數(shù): 31/70頁
文件大?。?/td> 341K
代理商: ISP1181A
Philips Semiconductors
ISP1181A
Full-speed USB peripheral controller
Product data
Rev. 05 — 08 December 2004
31 of 70
9397 750 13959
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12.1.7
Write/Read DMA Counter
This command accesses the DMA Counter Register, which consists of 2 bytes. The
bit allocation is given in
Table 26
. Writing to the register sets the number of bytes for a
DMA transfer. Reading the register returns the number of remaining bytes in the
current transfer. A bus reset will not change the programmed bit values.
The internal DMA counter is automatically reloaded from the DMA Counter Register
when DMA is re-enabled (DMAEN = 1). See
Section 12.1.6
for more details.
Code (Hex): F2/F3 —
write/read DMA Counter Register
Transaction —
write/read 2 bytes
Table 25:
Bit
15
DMA Configuration Register: bit description
Symbol
Description
CNTREN
A logic 1 enables the generation of an EOT condition, when the
DMA Counter Register reaches zero. Bus reset value:
unchanged.
SHORTP
A logic 1 enables short/empty packet mode. When receiving
(OUT endpoint) a short/empty packet an EOT condition is
generated. When transmitting (IN endpoint) this bit should be
cleared. Bus reset value: unchanged.
-
reserved
EPDIX[3:0]
Indicates the destination endpoint for DMA, see
Table 7
.
DMAEN
Writing a logic 1 enables DMA transfer, a logic 0 forces the end
of an ongoing DMA transfer. Reading this bit indicates whether
DMA is enabled (0 = DMA stopped, 1 = DMA enabled). This bit
is cleared by a bus reset.
-
reserved
BURSTL[1:0]
Selects the DMA burst length:
14
13 to 8
7 to 4
3
2
1 to 0
00 —
single-cycle mode (1 byte)
01 —
burst mode (4 bytes)
10 —
burst mode (8 bytes)
11 —
burst mode (16 bytes).
Bus reset value: unchanged.
Table 26:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
DMA Counter Register: bit allocation
15
14
13
12
DMACRH[7:0]
0
R/W
4
DMACRL[7:0]
0
R/W
11
10
9
8
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
3
R/W
2
R/W
1
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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