參數(shù)資料
型號: ISP1181A
廠商: NXP Semiconductors N.V.
英文描述: Full-speed Universal Serial Bus peripheral controller
中文描述: 全速通用串行總線外設(shè)控制器
文件頁數(shù): 40/70頁
文件大?。?/td> 341K
代理商: ISP1181A
Philips Semiconductors
ISP1181A
Full-speed USB peripheral controller
Product data
Rev. 05 — 08 December 2004
40 of 70
9397 750 13959
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12.3.6
Read Interrupt Register
This command indicates the sources of interrupts as stored in the 4-byte Interrupt
Register. Each individual endpoint has its own interrupt bit. The bit allocation of the
Interrupt Register is shown in
Table 48
. Bit BUSTATUS is used to verify the current
bus status in the interrupt service routine. Interrupts are enabled via the Interrupt
Enable Register, see
Section 12.1.5
.
While reading the interrupt register, read all the 4 bytes completely.
Code (Hex): C0 —
read interrupt register
Transaction —
read 4 bytes
Bit
Symbol
Reset
Access
7
6
5
4
3
2
1
0
CHIPIDL[7:0]
41H
R
R
R
R
R
R
R
R
Table 47:
Bit
15 to 8
7 to 0
Chip ID Register: bit description
Symbol
CHIPIDH[7:0]
CHIPIDL[7:0]
Description
chip ID code (81H)
silicon version (41H, with 41H representing the BCD encoded
version number)
Table 48:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Interrupt Register: bit allocation
31
30
29
28
27
26
25
24
reserved
0
R
23
0
R
22
0
R
21
0
R
20
0
R
19
0
R
18
EP9
0
R
10
EP1
0
R
2
0
R
17
EP8
0
R
9
EP0IN
0
R
1
RESUME
0
R
0
R
16
EP7
0
R
8
EP14
0
R
15
EP6
0
R
7
EP13
0
R
14
EP5
0
R
6
reserved
0
R
EP12
0
R
13
EP4
0
R
5
PSOF
0
R
EP11
0
R
12
EP3
0
R
4
SOF
0
R
EP10
0
R
11
EP2
0
R
3
EOT
0
R
EP0OUT
0
R
0
RESET
0
R
BUSTATUS
0
R
SUSPND
0
R
Table 49:
Bit
31 to 24
23 to 10
9
Interrupt Register: bit description
Symbol
Description
-
reserved
EP14 to EP1
A logic 1 indicates the interrupt source(s): endpoint 14 to 1.
EP0IN
A logic 1 indicates the interrupt source: control IN endpoint.
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