參數(shù)資料
型號(hào)： ISP1181
廠商： NXP Semiconductors N.V.
英文描述： Full-speed Universal Serial Bus Interface Device(全速通用串行總線接口器件)
中文描述： 全速通用串行總線接口設(shè)備（全速通用串行總線接口器件）
文件頁(yè)數(shù)： 26/69頁(yè)
文件大?。?/td> 1655K
代理商： ISP1181
Philips Semiconductors
ISP1181
Full-speed USB interface
Objective specification
Rev. 01 — 13 March 2000
26 of 69
9397 750 06896
Philips Electronics N.V. 2000. All rights reserved.
12.1.2
Write/Read Device Address
This command is used to set the USB assigned address in the Address Register and
enable the USB device. The Address Register bit allocation is shown in
Table 18
.
A USB bus reset sets the device address to 00H and enables the device. In response
to the standard USB request Set Address the firmware must issue a Write Device
Address command, followed by sending an empty packet to the host. The
new
device
address is activated when the host acknowledges the empty packet.
Code (Hex): B6/B7 —
write/read Address Register
Transaction —
write/read 1 byte
12.1.3
Write/Read Mode Register
This command is used to access the ISP1181 Mode Register, which consists of
1 byte (bit allocation: see
Table 19
). In 16-bit bus mode the upper byte is ignored.
The Mode Register controls the DMA bus width, resume and suspend modes,
interrupt activity, GoodLink signalling and SoftConnect operation. It can be used to
enable debug mode, where all errors and Not Acknowledge (NAK) conditions will
generate an interrupt.
Table 16: Endpoint Configuration Register: bit allocation
Bit
7
Symbol
FIFOEN
Reset
0
Access
R/W
6
5
4
3
2
1
0
EPDIR
0
R/W
DBLBUF
0
R/W
FFOISO
0
R/W
FFOSZ[3:0]
0
0
0
0
R/W
R/W
R/W
R/W
Table 17: Endpoint Configuration Register: bit description
Bit
Symbol
Description
7
FIFOEN
A logic 1 indicates an enabled FIFO with allocated memory.
A logic 0 indicates a disabled FIFO (no bytes allocated).
6
EPDIR
This bit defines the endpoint direction (0 = OUT, 1 = IN); it also
determines the DMA transfer direction (0 = read, 1 = write)
5
DBLBUF
A logic 1 indicates that this endpoint has double buffering.
4
FFOISO
A logic 1 indicates an isochronous endpoint. A logic 0 indicates
a bulk or interrupt endpoint.
3 to 0
FFOSZ[3:0]
Selects the FIFO size according to
Table 5
Table 18: Address Register: bit allocation
Bit
7
Symbol
DEVEN
Reset
0
Access
R/W
6
5
4
3
2
1
0
DEVADR[6:0]
0
R/W
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Table 19: Address Register: bit description
Bit
Symbol
7
DEVEN
6 to 0
DEVADR[6:0]
Description
A logic 1 enables the device.
This field specifies the USB device address.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1181A 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller
ISP1181ABS 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller
ISP1181ABS,518 功能描述:USB 接口集成電路 USB 1.1 ADV DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1181ABS,551 功能描述:USB 接口集成電路 USB 1.1 ADVANCED DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1181ABS,557 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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