參數(shù)資料
型號(hào): ISP1161ABD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 66/134頁
文件大小: 587K
代理商: ISP1161ABD
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
66 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10.4.2
HcDMAConfiguration register (R/W: 21H/A1H)
Code (Hex): 21 —
read
Code (Hex): A1 —
write
5
DREQOutputPolarity
0 —
active LOW
1 —
active HIGH. Power-up value
01 —
16 bits
4 to 3
DataBusWidth[1:0]
Others —
reserved
0 —
active LOW. Power-up value
2
InterruptOutputPolarity
1 —
active HIGH
0 —
interrupt is level-triggered. Power-up value
1
InterruptPinTrigger
1 —
interrupt is edge-triggered
0 —
INT1 is disabled. Power-up value
0
InterruptPinEnable
1 —
pin INT1 is enabled
Table 37:
Bit
HcHardwareConfiguration register: bit description
…continued
Symbol
Description
Table 38:
Bit
Symbol
Reset
Access
Bit
Symbol
HcDMAConfiguration register: bit allocation
15
14
13
12
11
10
9
8
reserved
0
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
4
DMA
Enable
0
R/W
R/W
3
R/W
2
R/W
1
R/W
0
reserved
BurstLen[1:0]
reserved
DMACount
erSelect
0
R/W
ITL_ATL_
DataSelect
0
R/W
DMARead
WriteSelect
0
R/W
Reset
Access
0
0
0
0
R/W
R/W
R/W
R/W
Table 39:
Bit
15 to 7
6 to 5
HcDMAConfiguration register: bit description
Symbol
Description
-
reserved
BurstLen[1:0]
00 —
single-cycle burst DMA
01 —
4-cycle burst DMA
10 —
8-cycle burst DMA
11 —
reserved
0 —
DMA is terminated
4
DMAEnable
1 —
DMA is enabled
This bit will be reset to zero when DMA transfer is completed
reserved
3
-
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