參數(shù)資料
型號: ISP1161ABD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 58/134頁
文件大?。?/td> 587K
代理商: ISP1161ABD
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
58 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Code (Hex): 13 —
read
Code (Hex): 93 —
write
Table 30:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcRhDescriptorB register: bit allocation
31
30
29
28
27
26
25
24
reserved
N/A
R
23
N/A
R
22
N/A
R
21
N/A
R
20
N/A
R
19
N/A
R
18
N/A
R
17
N/A
R
16
reserved
N/A
R
13
PPCM[2:0]
IS
R/W
9
N/A
R
15
N/A
R
14
N/A
R
12
N/A
R
11
IS
IS
R/W
10
R/W
8
reserved
N/A
R
7
N/A
R
6
N/A
R
5
N/A
R
4
N/A
R
3
N/A
R
2
N/A
R
1
N/A
R
0
reserved
N/A
R
DR[2:0]
IS
R/W
N/A
R
N/A
R
N/A
R
N/A
R
IS
IS
R/W
R/W
Table 31:
Bit
31 to 19
18 to 16
HcRhDescriptorB register: bit description
Symbol
Description
-
reserved
PPCM[2:0]
PortPowerControlMask:
Each bit indicates whether a port is
affected by a global power control command when
PowerSwitchingMode is set. When set, the port’s power state is
only affected by per-port power control (Set/ClearPortPower).
When cleared, the port is controlled by the global power switch
(Set/ClearGlobalPower). If the device is configured to global
switching mode (PowerSwitchingMode = 0), this field is not valid.
Bit 0 —
reserved
Bit 1 —
Ganged-power mask on Port #1
Bit 2 —
Ganged-power mask on Port #2
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