參數(shù)資料
型號(hào): ISP1161ABD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 19/134頁
文件大?。?/td> 587K
代理商: ISP1161ABD
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
19 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.6.2
HC’s interrupt output pin (INT1)
To program the four configuration modes of the HC’s interrupt output signal (INT1),
set bits InterruptPinTrigger and InterruptOutputPolarity of the
HcHardwareConfiguration register (20H - read, A0H - write). Bit InterruptPinEnable is
used as the master enable setting for pin INT1.
INT1 has many associated interrupt events, as shown as in
Figure 20
.
The interrupt events of the Hc
μ
PInterrupt register (24H - read, A4H - write) changes
the status of pin INT1 when the corresponding bits of the Hc
μ
PInterruptEnable
register (25H - read, A5H - write) and pin INT1’s global enable bit (InterruptPinEnable
of the HcHardwareConfiguration register) are all set to enable status.
However, events that come from the HcInterruptStatus register (03H - read, 83H -
write) affect only the OPR_Reg bit of the Hc
μ
PInterrupt register. They cannot directly
change the status of pin INT1.
Fig 19. Interrupt pin operating modes.
MGT944
INT active
INT active
clear or disable INT
Mode 1 level triggered, active HIGH
INT
INT
166 ns
Mode 2 edge triggered, active LOW
INT active
INT
166 ns
Mode 3 edge triggered, active HIGH
INT active
clear or disable INT
Mode 0 level triggered, active LOW
INT
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