參數(shù)資料
型號： ISP1161A
廠商： NXP Semiconductors N.V.
英文描述： Full-speed Universal Serial Bus single-chip host and device controller
中文描述： 全速通用串行總線的單芯片主機(jī)和設(shè)備控制器
文件頁數(shù)： 32/134頁
文件大小： 587K
代理商： ISP1161A
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
32 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.4.3
Operation and C program example
Figure 29
shows the block diagram for internal FIFO buffer RAM operations in PIO
mode. The ISP1161A provides one register as the access port for each buffer RAM.
For the ITL buffer RAM, the access port is the ITLBufferPort register (40H - read, C0H
- write). For the ATL buffer RAM, the access port is the ATLBufferPort register (41H -
read, C1H - write). The buffer RAM is an array of bytes (8 bits) while the access port
is a 16-bit register. Therefore, each read/write operation on the port accesses two
consecutive memory locations, incrementing the pointer of the internal buffer RAM by
two. The
lower
byte of the access port register corresponds to the data byte at the
even
location of the buffer RAM, and the
upper
byte corresponds to the next data
byte at the
odd
location of the buffer RAM. Regardless of the number of data bytes to
be transferred, the command code must be issued merely once, and it will be
followed by a number of accesses of the data port (see
Section 8.4
).
When the pointer of the buffer RAM reaches the value of the HcTransferCounter
register, an internal EOT signal will be generated to set bit 2, AllEOTInterrupt, of the
Hc
μ
Pinterrupt register and update the HcBufferStatus register, to indicate that the
whole data transfer has been completed.
For ITL buffer RAM, every Start Of Frame (SOF) signal (1 ms) will cause toggling
between ITL0 and ITL1, but this depends on the buffer status. If both ITL0BufferFull
and ITL1BufferFull of the HcBufferStatus register are already logic 1, meaning that
both ITL0 and ITL1 buffer RAMs are full, the toggling will not happen. In this case, the
microprocessor will always have access to ITL1.
Fig 28. PTD data with DWORD alignment in buffer RAM.
MGT953
payload data
(14 bytes)
PTD
(8 bytes)
PTD
(8 bytes)
00H
top
08H
15H
18H
20H
payload data
RAM buffer
相關(guān)PDF資料
PDF描述
ISP1161ABD Full-speed Universal Serial Bus single-chip host and device controller
ISP1161ABM Full-speed Universal Serial Bus single-chip host and device controller
ISP1161 Full-speed Universal Serial Bus single-chip host and device controller
ISP1161A1 Universal Serial Bus single-chip host and device controller
ISP1161A1BD Universal Serial Bus single-chip host and device controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1161A1 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal Serial Bus single-chip host and device controller
ISP1161A1BD 功能描述:IC USB HOST/DEVICE CTRLR 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
ISP1161A1BD,118 功能描述:USB 接口集成電路 USB1.1 HOST &DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161A1BD,151 功能描述:USB 接口集成電路 USB1.1 HOST &DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161A1BD,157 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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