Philips Electronics N.V. 2001.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 3 July 2001
Document order number: 9397 750 08313
Contents
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
1
2
3
4
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
8.1
8.2
8.3
General description
. . . . . . . . . . . . . . . . . . . . . . 1
Features
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Applications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering information
. . . . . . . . . . . . . . . . . . . . . 4
Block diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pinning information
. . . . . . . . . . . . . . . . . . . . . . 7
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional description
. . . . . . . . . . . . . . . . . . 11
PLL clock multiplier. . . . . . . . . . . . . . . . . . . . . 11
Bit clock recovery . . . . . . . . . . . . . . . . . . . . . . 11
Analog transceivers . . . . . . . . . . . . . . . . . . . . 11
Philips Serial Interface Engine (SIE). . . . . . . . 11
SoftConnect (in DC) . . . . . . . . . . . . . . . . . . . . 11
GoodLink (in DC) . . . . . . . . . . . . . . . . . . . . . . 12
Suspend and wakeup (in DC). . . . . . . . . . . . . 12
Microprocessor bus interface
. . . . . . . . . . . . . 12
I/O addressing mode . . . . . . . . . . . . . . . . . . . 12
DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Microprocessor read/write ISP1161’s
internal control registers by PIO mode . . . . . 14
Microprocessor read/write ISP1161’s
internal FIFO buffer RAM by PIO mode. . . . . 17
Microprocessor read/write ISP1161’s
internal FIFO buffer RAM by DMA mode. . . . 17
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
The USB host controller (HC)
. . . . . . . . . . . . . 22
The HC’s four USB states. . . . . . . . . . . . . . . . 22
Generating USB traffic . . . . . . . . . . . . . . . . . . 22
PTD data structure . . . . . . . . . . . . . . . . . . . . . 24
HC’s internal FIFO buffer RAM structure . . . . 27
HC’s operational model . . . . . . . . . . . . . . . . . 33
Microprocessor loading. . . . . . . . . . . . . . . . . . 36
Internal 15 kW pull-down resistors for
downstream ports . . . . . . . . . . . . . . . . . . . . . 36
Overcurrent detection and power switching
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Suspend and wakeup (in HC)
. . . . . . . . . . . . . 40
HC suspended state. . . . . . . . . . . . . . . . . . . . 40
HC wakeup from suspended state . . . . . . . . . 41
The USB device controller (DC)
. . . . . . . . . . . 42
DC data transfer operation . . . . . . . . . . . . . . . 42
Device DMA transfer. . . . . . . . . . . . . . . . . . . . 43
Endpoint descriptions . . . . . . . . . . . . . . . . . . . 44
DMA transfer for the Device Controller
. . . . . 48
Selecting an endpoint for DMA transfer . . . . . 48
8237 compatible mode . . . . . . . . . . . . . . . . . . 49
DACK-only mode . . . . . . . . . . . . . . . . . . . . . . 50
8.4
8.5
8.6
9
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
10
10.1
10.2
11
11.1
11.2
11.3
12
12.1
12.2
12.3
12.4
13
13.1
13.2
13.3
13.4
13.5
13.6
14
14.1
14.2
14.3
15
16
17
18
19
20
20.1
20.2
20.3
21
21.1
21.2
End-Of-Transfer conditions. . . . . . . . . . . . . . . 51
HC registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . 53
HC control and status registers. . . . . . . . . . . . 54
HC frame counter registers. . . . . . . . . . . . . . . 62
HC Root Hub registers . . . . . . . . . . . . . . . . . . 66
HC DMA and interrupt control registers . . . . . 76
HC miscellaneous registers . . . . . . . . . . . . . . 81
HC buffer RAM control registers. . . . . . . . . . . 82
DC commands and registers
. . . . . . . . . . . . . 86
Initialization commands. . . . . . . . . . . . . . . . . . 89
Data flow commands . . . . . . . . . . . . . . . . . . . 96
General commands. . . . . . . . . . . . . . . . . . . . 100
Reset
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Power supply
. . . . . . . . . . . . . . . . . . . . . . . . . 105
External clock input
. . . . . . . . . . . . . . . . . . . . 106
Limiting values
. . . . . . . . . . . . . . . . . . . . . . . . 107
Static characteristics
. . . . . . . . . . . . . . . . . . . 108
Dynamic characteristics
. . . . . . . . . . . . . . . . 111
Timing symbols. . . . . . . . . . . . . . . . . . . . . . . 112
Parallel I/O timing . . . . . . . . . . . . . . . . . . . . . 113
DMA interface timing. . . . . . . . . . . . . . . . . . . 114
Application information
. . . . . . . . . . . . . . . . . 119
Typical interface circuit . . . . . . . . . . . . . . . . . 119
Interfacing a ISP1161 with a SH7709
RISC processor . . . . . . . . . . . . . . . . . . . . . . 120
Typical software model . . . . . . . . . . . . . . . . . 120
Test information
. . . . . . . . . . . . . . . . . . . . . . . 121
Package outline
. . . . . . . . . . . . . . . . . . . . . . . 123
Soldering
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 125
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 125
Manual soldering. . . . . . . . . . . . . . . . . . . . . . 126
Package related soldering information . . . . . 126
Revision history
. . . . . . . . . . . . . . . . . . . . . . . 126
Data sheet status
. . . . . . . . . . . . . . . . . . . . . . 127
Definitions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Disclaimers
. . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Trademarks
. . . . . . . . . . . . . . . . . . . . . . . . . . . 127
21.3
22
23
24
24.1
24.2
24.3
24.4
24.5
25
26
27
28
29