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參數(shù)資料
| 型號： | IS3-L67132L-55 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | SRAM |
| 英文描述： | 2K X 8 DUAL-PORT SRAM, 55 ns, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大小： | 178K |
| 代理商： | IS3-L67132L-55 |
L67132/L67142
Rev. D (19 Fev. 97)
4
MATRA MHS
Truth Table
Table 1 : Non Contention Read/Write Control(4)
LEFT OR RIGHT PORT(1)
FUNCTION
R/W
CS
OE
D0–7
FUNCTION
X
H
X
Z
Port Disabled and in Power Down Mode. ICCSB or ICCSB1
L
X
DATAIN
Data on Port Written into memory(2)
H
L
DATAOUT
Data in Memory Output on Port(3)
H
L
H
Z
High Impedance Outputs
Notes :
1. AOL – A10L ≠ A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. H = HIGH, L = LOW, X = DON’T CARE, Z = HIGH IMPEDANCE.
Table 2 : Arbitration(5)
LEFT PORT
RIGHT PORT
FLAGS
FUNCTION
CSL
A0L – A10L
CSR
A0L – A10R
BUSYL
BUSYR
FUNCTION
H
X
H
X
H
No Contention
L
Any
H
X
H
No Contention
H
X
L
Any
H
No Contention
L
≠ A0R – A10R
L
≠ A0L – A10L
H
No Contention
ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH
L
LV5R
L
LV5R
H
L
L–Port Wins
L
RV5L
L
RV5L
L
H
R–Port Wins
L
Same
L
Same
H
L
Arbitration Resolved
L
Same
L
Same
L
H
Arbitration Resolved
CS ARBITRATION WITH ADDRESS MATCH BEFORE CS
LL5R
= A0R – A10R
LL5R
= A0L – A10L
H
L
L–Port Wins
RL5L
= A0R – A10R
RL5L
= A0L – A10L
L
H
R–Port Wins
LW5R
= A0R – A10R
LW5R
= A0L – A10L
H
L
Arbitration Resolved
LW5R
= A0R – A10R
LW5R
= A0L – A10L
L
H
Arbitration Resolved
Notes :
5. X = DON’T CARE, L = LOW, H = HIGH.
LV5R = Left Address Valid
≥ 5 ns before right address.
RV5L = Right address Valid
≥ 5 ns before left address.
Same = Left and Right Addresses match within 5 ns of each other.
LL5R = Left CS = LOW
≥ 5 ns before Right CS.
RL5L = Right CS = LOW
≥ 5 ns before left CS.
LW5R = Left and Right CS = LOW within 5 ns of each other.
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