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參數(shù)資料
| 型號： | IS3-L67132L-55 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | SRAM |
| 英文描述： | 2K X 8 DUAL-PORT SRAM, 55 ns, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 178K |
| 代理商： | IS3-L67132L-55 |
L67132/L67142
Rev. D (19 Fev. 97)
7
MATRA MHS
AC Parameters
READ CYCLE
PARAMETER
L67132–45
L67142–45
L67132–55
L67142–55
L67132–70
L67142–70
UNIT
SYMBOL
PARAMETER
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
UNIT
SYMBOL
(19)
SYMBOL
(20)
PRELIMINARY
TAVAVR
tRC
Read cycle time
45
–
55
–
70
–
ns
TAVQV
tAA
Address access time
–
45
–
55
–
70
ns
TELQV
tACS
Chip Select access time (18)
–
45
–
55
–
70
ns
TGLQV
tAOE
Output enable access time
–
30
–
35
–
40
ns
TAVQX
tOH
Output hold from address change
0
–
0
–
0
–
ns
TELQZ
tLZ
Output low Z time (16, 17)
5
–
5
–
5
–
ns
TEHQZ
tHZ
Output high Z time (16, 17)
–
20
–
30
–
35
ns
TPU
tPU
Chip Select to power up time (17)
0
–
0
–
0
–
ns
TPD
tPD
Chip disable to power down time (17)
–
50
–
50
–
50
ns
Notes :
16. Transition is measured
± 500 mV from low or high impedance voltage with load (figures 1 and 2).
17. This parameter is guaranteed but not tested.
18. To access RAM CS = VIL.
19. STD symbol.
20. ALT symbol.
Timing Waveform of Read Cycle no 1, Either Side (21, 22, 24)
Timing Waveform of Read Cycle no 2, Either Side (21, 23, 25)
Notes :
21. R/W is high for read cycles.
22. Device is continuously enabled, CS = VIL.
23. Addresses valid prior to or coincident with CS transition low.
24. OE = VIL.
25. To access RAM, CS = VIL.
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