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參數(shù)資料
| 型號(hào)： | IS3-L67132L-55 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | SRAM |
| 英文描述： | 2K X 8 DUAL-PORT SRAM, 55 ns, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 178K |
| 代理商： | IS3-L67132L-55 |
L67132/L67142
Rev. D (19 Fev. 97)
6
MATRA MHS
Data-Retention Mode
MHS CMOS RAMs are designed with battery backup in
mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules insure
data retention :
1 – Chip select (CS) must be held high during data
retention ; within Vcc to VCCDR.
2 – CS must be kept between VCC – 0.2 V and 70 % of Vcc
during the power up and power down transitions.
3 – The RAM can begin operation > tRC after Vcc
reaches the minimum operating voltage (3 volts).
Timing
MAX
PARAMETER
TEST CONDITIONS (14)
COM
MIL
IND
AUTO
UNIT
ICCDR1
@ VCCDR = 2 V
10
20
A
Notes : 14. CS = Vcc, Vin = Gnd to Vcc.
AC Test Conditions
Input Pulse Levels : GND to 3.0 V
Input Rise/Fall Times : 5 ns
Input Timing Reference Levels : 1.5 V
Figure 1. Output Load.
Output Reference Levels : 1.5 V
Output Load : see figures 1, 2
Figure 2. Output load.
(For tHZ, tLZ, tWZ, and tOW)
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