19
IR1110
ADVANCE INFORMATION
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After the above delay, the Voltage Dip Comparator is reset when the output of the Timing
Wave Intersect Comparator goes high, which occurs when the line voltage returns to normal. Q2
is momentarily turned ON, allowing the voltage on C
HOLD
to reset. Q4 is turned ON, unclamping
the Ramp, and Q5 is turned OFF, unclamping C
ERR
. Ramp-back of the bus voltage now occurs.
When the output of the Voltage Dip Comparator is low, Q1 is turned OFF. R
PKD
is then
disconnected from ground, allowing C
PK
to hold its charge during the voltage dip.
Voltage Dip during Dynamic Regulation
If |V
BREF
| is rapidly decreased by a sufficient amount, this may cause a decrease of bus
voltage that will set the Voltage Dip Comparator and cause the bus voltage to undershoot.
Since the timing waves are still present, the output of the Timing Wave Intersect Com-
parator remains high, and the Voltage Dip Comparator will be quickly reset, ramping the bus
voltage back to the set value.
This undershoot of the bus voltage will be avoided if changes in |V
BUSREF
| are controlled at
a rate that does not significantly
“
overtake
”
the discharge rate of C
HOLD
, which is set by C
HOLD
,
R
DIP1
and R
DIP2
.
Undervoltage and Undervoltage Lockout Comparators
The UV Comparator delivers a high output when V
DD
exceeds the internally fixed
reference value.
The UV Lockout Comparator delivers a high output when the voltage C
UVLO
exceeds a
nominal value of about 1.5V. C
UVLO
is driven from a current source of approximately 2uA.
The outputs of the UV and UV Lockout Comparators are ANDed. When the output of
either comparator is low, the SCR firing pulses are inhibited, and Q4 is turned OFF, clamping
the ramp.
One Phase Loss Circuit
A train of fixed duration (nominal 2msec) pulses are delivered to the gate of Q6, if one
input phase is missing. With 1-phase shutdown enabled, each 1-phase loss pulse discharges
C
UVLO
by about 1.5V. During the third successive pulse, C
UVLO
is discharged sufficiently that the
output of the UV Lockout Comparator goes low.
The principle of generation of the 1-phase loss pulses is illustrated in Figure 8. These
pulses are generated;
(a) during one phase loss
(b) briefly during abnormal dips of line voltage
(c) if the DC bus is short circuited and the SCR firing angle is advanced by more than about 30
°
from the zero crossing of the line voltage
With 1-phase shutdown enabled, generation of
“
1-phase loss
”
pulses under condition (b)
reinforces the ramp clamp function. Under condition (c) it results in automatic limiting of short
circuit current, as explained later.
The 1-phase loss pulses at 1PHLED output follow the output of the 1-Phase Loss Circuit.