參數(shù)資料
型號(hào)： IR1110
廠商： International Rectifier
英文描述： SOFT START CONTROLLER IC
中文描述： 軟起動(dòng)控制器芯片
文件頁(yè)數(shù)： 16/32頁(yè)
文件大?。?/td> 227K
代理商： IR1110
16
IR1110
ADVANCE INFORMATION
www.irf.com
During transient line voltage outage, the Ramp Clamp is enabled. V
RAMP
is then forced into
the above relationship with V
BUSO
. The amplitude of V
RAMP
is thereby preset when the line voltage
returns, so that the bus voltage ramps back without significant delay, but also without unaccept-
able jump of bus voltage.
The choice of R
CLAMP2
/R
CLAMP1
is a compromise between the delay in starting ramp-back
of the output voltage, and the initial jump of voltage when the line voltage returns after outage.
With an inductive filter at the output of the rectifier, R
CLAMP2
/R
CLAMP1
can be set to a higher
value than with just a bus capacitor, to minimize the response time in restoring the DC bus voltage
after line outage.
Timing Wave Reference Summing Amplifier
The output of the Timing Wave Reference Summing Amplifier is the Timing Wave Refer-
ence; this is essentially the difference between VPK and VRAMP, so long as the output of Error
Amplifier 2 is zero. Thus, when VRAMP is zero, the Timing Wave Reference voltage is essentially
equal to VPK, and SCR firing angle is close to the zero crossing of the line-to-line voltage; as the
ramp increases, the firing angle advances. Refer to Figure 5.
Closed Loop Bus Voltage Regulation
The bus voltage reference, -V
BUSREF
, sets the amplitude of the steady bus voltage. This
external reference is negative with respect to
“
ground
”
, i.e., with respect to the positive output
terminal of the rectifier bridge. This facilitates derivation of V
BUSREF
, if required, via a level shift
circuit that is referenced to the negative DC bus.
If bus voltage control is not used, and steady operation at the maximum DC bus voltage
only is required, V
BUSREF
should be connected to V
SS
.
The Inverting Amplifier inverts the reference to +V
BUSREF
. If the maximum possible value
of |V
BUSO
| is less than |V
BUSREF
|, the voltage regulation loop is inactive. The average output of
Error Amplifier 1 is always negative, the voltage across C
ERR
is clamped to zero by the parallel
diode, the output of Error Amplifier 2 is always zero, and the bus voltage ramps to the maximum
possible value.
If |V
BUSO
| becomes greater than |V
BUSREF
|, the average output of Error Amplifier 1 becomes
positive. This output is filtered by R
ERR
and C
ERR
, and a smooth voltage representing the dc error
between |V
BUSO
| and |V
BUSREF
| appears across C
ERR
. This voltage is amplified by Error Amplifier 2,
and fed as an input to the Timing Wave Reference Summing Amplifier. The added input to the
Timing Wave Reference Summing Amplifier increases the Timing Wave Reference, delaying the
SCR firing angle, and forcing the bus voltage to a value proportional to |V
BUSREF
|.
Since the voltage regulation circuit becomes active only when |V
BUSO
| exceeds |V
BUSREF
|,
the ramp rate during power-up of the bus voltage is determined solely by the rate of increase of
V
RAMP
. If |V
BUSO
| starts to exceed |V
BUSREF
| during ramp up, the output of Error Amplifier 2 starts to
oppose the increasing ramp voltage, restraining further increase of bus voltage. Some overshoot
occurs while the ramp continues to increase to V
PK
.
In normal operation, after ramp up, the bus voltage is no longer controlled by the ramp,
unless an event occurs that causes the ramp to be clamped.
Rise and fall rates of the bus voltage that are driven by changes in |V
BUSREF
| in normal
operation are determined by the applied rise and fall rates of |V
BUSREF
|, and by the characteristics
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