參數(shù)資料
型號(hào)： IR1110
廠商： International Rectifier
英文描述： SOFT START CONTROLLER IC
中文描述： 軟起動(dòng)控制器芯片
文件頁數(shù)： 18/32頁
文件大?。?/td> 227K
代理商： IR1110
18
IR1110
ADVANCE INFORMATION
www.irf.com
Voltage Dip Circuit
The DC bus voltage will fall if the input line voltage dips or is lost.
For short period outage, the bus capacitor voltage may hold up sufficiently that ramp back
when the line voltage returns is unnecessary.
If the bus voltage falls below a preset level, then the ramp is automatically clamped, in
order to avoid an unacceptable jump of bus voltage when the line returns.
The Voltage Dip Comparator monitors dips on the DC bus voltage. The bus voltage, -
V
BUSO
, is captured on C
HOLD
. The Voltage Dip Comparator compares a fraction of this captured
voltage, with -V
BUSO
.
In normal operation, |kV
BUSO
| is less than |V
BUSO
|, and the output of the Voltage Dip
Comparator is high. When a short line outage occurs, the voltage captured on C
HOLD
remains
substantially equal to the pre-dip value, while |V
BUSO
| starts to decrease as the bus capacitor
discharges. If |V
BUSO
| dips to less than k x V
BUS1
, where V
BUS1
is the initial bus voltage, the output
of the Voltage Dip Comparator latches low, Q4 is switched off and the ramp is clamped. Q5 is
turned ON, discharging the voltage on C
ERR
.
R
DIP2
kV
BUS1
= x V
BUS1
- (0.1 V
LLMAX
)
R
DIP1
+ R
DIP2
where V
LLMAX
is the maximum design value of rms line voltage
The Voltage Dip Comparator remains low for a minimum period, T
DELAY2
, of approxmately 5
milliseconds, set by C
BDIP1
. Thereafter, so long as the line voltage is absent or remains abnormally
low, the output of the Timing Wave Intersect Comparator remains low, keeping the Voltage Dip
Comparator latched low.
T
DELAY2
in milliseconds is approximately equal to (.0015 X C
BDIP1
pF). Thus for C
BDIP1
=
3300pF, T
DELAY2
is about 5 milliseconds.
The total delay, T
DELAY_TOT
, between the point of initiation of the line voltage outage, and
the point at which the voltage dip comparator is allowed to reset, must be at least 10 milliseconds.
T
DELAY_TOT
is the sum of T
DELAY1
and T
DELAY2
. T
DELAY1
is the time between the point of
initiation of the line outage, and the point at which the bus voltage falls to kVBUS1. Thus, with
T
DELAY2
set at 5 milliseconds, the minimum allowed value for T
DELAY1
is 5 milliseconds.
If the bus capacitor is sized so that, at maximum DC load current, the bus voltage will fall
to kVBUS1 in less than 5 milliseconds, then C
BDIP1
should be increased to ensure that T
DELAY_TOT
cannot fall below 10 milliseconds.
If C
BDIP1
is increased so that T
DELAY2
is at least 10 milliseconds, T
DELAY_TOT
will always be
greater than 10 milliseconds. This is an inherently safe design approach, though it does add a few
milliseconds of potentially unnecessary delay, before ramp-back can commence during a short
line outage.
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