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參數(shù)資料
| 型號： | HY5V52CLF-6 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 8M X 32 SYNCHRONOUS DRAM, 5.4 ns, PBGA90 |
| 封裝： | 0.80 MM PITCH, FBGA-90 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 161K |
| 代理商： | HY5V52CLF-6 |
Rev. 0.7 / Dec. 2003
10
HY5V52CF
COMMAND TRUTH TABLE
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don
′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1.
4. This command stops a full-page burst operation, and is illegal otherwise. Full page burst continues untill this command is input.
When data input/output is completed for full-page of data, it automatically returns to the start address and input/output is performed repeatedly.
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
ADDR
A10/
AP
BA
Note
Mode Register Set
H
X
L
X
OP code
No Operation
H
X
HX
X
XX
L
HHH
Bank Active
H
X
L
H
X
RA
V
Read
H
X
LHLH
X
CA
L
V
Read with Autoprecharge
H
Write
HX
L
H
L
X
CA
L
V
Write with Autoprecharge
H
Precharge All Banks
HX
L
H
L
X
HX
Precharge selected Bank
LV
Burst Stop
H
X
L
H
L
X
4
DQM
H
X
V
X
Auto Refresh
H
L
H
X
Burst-Read-Single-WRITE
H
X
L
X
A9 Pin High
(Other Pins OP code)
MRS
Mode
Self Refresh1
Entry
H
L
H
X
Exit
L
H
HX
X
L
HHH
Precharge power
down
Entry
H
L
HX
X
L
HHH
Exit
L
H
HX
X
L
HHH
Clock
Suspend
Entry
H
L
HX
X
LV
V
Exit
L
H
X
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