參數(shù)資料
型號: HY5PS1G831ALFP-Y5
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 128M X 8 DDR DRAM, PBGA68
封裝: FBGA-68
文件頁數(shù): 31/36頁
文件大?。?/td> 574K
代理商: HY5PS1G831ALFP-Y5
Rev. 0.7 / Oct. 2007
4
HY5PS1G431A(L)FP
HY5PS1G831A(L)FP
HY5PS1G1631A(L)FP
1.1 Device Features & Ordering Information
1.1.1 Key Features
VDD=1.8V +/- 0.1V
VDDQ=1.8 +/- 0.1V
All inputs and outputs are compatible with SSTL_18 interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
Differential Data Strobe (DQS, DQS)
Data outputs on DQS, DQS edges when read (edged DQ)
Data inputs on DQS centers when write(centered DQ)
On chip DLL align DQ, DQS and DQS transition with CK transition
DM mask write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
Programmable CAS latency 3, 4 and 5 supported
Programmable additive latency 0, 1, 2, 3 and 4supported
Programmable burst length 4/8 with both nibble sequential and interleave mode
Internal eight bank operations with single pulsed RAS
Auto refresh and self refresh supported
tRAS lockout supported
8K refresh cycles /64ms
JEDEC standard 68ball FBGA(x4/x8) , 92ball FBGA(x16)
Full strength driver option controlled by EMRS
On Die Termination supported
Off Chip Driver Impedance Adjustment supported
Read Data Strobe supported (x8 only)
Self-Refresh High Temperature Entry
Ordering Information
Part No.
Configuration Package
HY5PS1G431A(L)FP-XX*
256Mx4
68 Ball
HY5PS1G831A(L)FP-XX*
128Mx8
HY5PS1G1631A(L)FP-XX*
64Mx16
92 Ball
Operating Frequency
Grade
tCK(ns)
CL
tRCD
tRP
Unit
E3
53
3
Clk
C4
3.75
4
Clk
Y5
35
5
Clk
Note:
XX* is the speed bin, refer to the Operation Frequency table for complete part number.
Hynix lead-free products are compliant to RoHS.
1. Description
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