參數(shù)資料
型號(hào): HY5PS1G831ALFP-Y5
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 128M X 8 DDR DRAM, PBGA68
封裝: FBGA-68
文件頁數(shù): 15/36頁
文件大?。?/td> 574K
代理商: HY5PS1G831ALFP-Y5
Rev. 0.7 / Oct. 2007
22
HY5PS1G431A(L)FP
HY5PS1G831A(L)FP
HY5PS1G1631A(L)FP
Parameter
Symbol
DDR2-400
DDR2-533
Unit
Note
min
max
min
max
Four Active Window for 1KB page size
products
tFAW
37.5
-
37.5
-
ns
Four Active Window for 2KB page size
products
tFAW
50
-50
-
CAS to CAS command delay
tCCD
2
tCK
Write recovery time
tWR
15
-15
-
ns
Auto precharge write recovery + precharge
time
tDAL
WR+tRP*
-
WR+tRP*
-
tCK
14
Internal write to read command delay
tWTR
10
-7.5
-
ns
24
Internal read to precharge command delay
tRTP
7.5
ns
3
Exit self refresh to a non-read command
tXSNR
tRFC + 10
ns
Exit self refresh to a read command
tXSRD
200
-
200
-
tCK
Exit precharge power down to any non-read
command
tXP
2
-
2
-
tCK
Exit active power down to read command
tXARD
2
tCK
1
Exit active power down to read command
(Slow exit, Lower power)
tXARDS
6 - AL
tCK
1, 2
CKE minimum pulse width
(high and low pulse width)
tCKE
3
tCK
ODT turn-on delay
tAOND
22
2
tCK
ODT turn-on
tAON
tAC(min)
tAC(max)+
1
tAC(min)
tAC(max)
+1
ns
16
ODT turn-on(Power-Down mode)
tAONPD
tAC(min)+
2
2tCK+
tAC(max)
+1
tAC(min)+
2
2tCK+tAC
(max)+1
ns
ODT turn-off delay
tAOFD
2.5
tCK
ODT turn-off
tAOF
tAC(min)
tAC(max)+
0.6
tAC(min)
tAC(max)
+ 0.6
ns
17
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min)+
2
2.5tCK+tA
C(max)+1
tAC(min)+
2
2.5tCK+tA
C(max)+1
ns
ODT to power down entry latency
tANPD
3
tCK
ODT power down exit latency
tAXPD
8
tCK
OCD drive mode output delay
tOIT
0
12
0
12
ns
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tDelay
tIS+tCK+tI
H
tIS+tCK+tI
H
ns
15
-Continued
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