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| 型號： | HW-V5-ML561-UNI-G-J |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 43/91頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVALUATION PLATFORM VIRTEX-5 |
| 產(chǎn)品變化通告： | Development Systems Discontinuation 16/Jan/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex®-5 LXT |
| 類型： | FPGA |
| 適用于相關(guān)產(chǎn)品： | XC5VLX50T-FFG1136 |
| 所含物品： | 評估平臺，線纜，CD，小型閃存卡，DDR2 DIMM，- 不包括電源 - |
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Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
48
DSP48E Switching Characteristics
Reset Delays
TRCO_FLAGS
Reset RST to FIFO Flags/Pointers(11)
1.10
1.26
1.48
ns, Max
Maximum Frequency
FMAX
Block RAM in all modes
550
500
450
MHz
FMAX_CASCADE
Block RAM in cascade configuration
500
450
400
MHz
FMAX_FIFO
FIFO in all modes
550
500
450
MHz
FMAX_ECC
Block RAM and FIFO in ECC configuration
415
375
325
MHz
Notes:
1.
TRACE will report all of these parameters as TRCKO_DO.
2.
TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters.
3.
These parameters also apply to synchronous FIFO with DO_REG = 0.
4.
TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters.
5.
These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
6.
TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR.
7.
TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT.
8.
The ADDR setup and hold must be met when EN is asserted even though WE is deasserted. Otherwise, block RAM data corruption is possible.
9.
TRCKO_DI includes both A and B inputs as well as the parity inputs of A and B.
10. These parameters also apply to RDEN.
11. TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
Table 69: DSP48E Switching Characteristics
Symbol
Description
Speed
Units
-3
-2
-1
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_{AA, BB, ACINA, BCINB}/
TDSPCKD_{AA, BB, ACINA, BCINB}
{A, B, ACIN, BCIN} input to {A, B}
register CLK
0.17
0.21
0.23
0.26
0.30
ns
TDSPDCK_CC/TDSPCKD_CC
C input to C register CLK
0.14
0.26
0.16
0.31
0.20
0.37
ns
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_{AM, BM, ACINM, BCINM}/
TDSPCKD_{AM, BM, ACINM, BCINM}
{A, B, ACIN, BCIN} input to M register
CLK
1.30
0.19
1.44
0.19
1.71
0.19
ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{AP, BP, ACINP, BCINP}_M/
TDSPCKD_{AP, BP, ACINP, BCINP}_M
{A, B, ACIN, BCIN} input to P register
CLK using multiplier
2.39
–0.30
2.74
–0.30
3.25
–0.30
ns
TDSPDCK_{AP, BP, ACINP, BCINP}_NM/
TDSPCKD_{AP, BP, ACINP, BCINP}_NM
{A, B, ACIN, BCIN} input to P register
CLK not using multiplier
1.35
–0.10
1.54
–0.10
1.83
–0.10
ns
TDSPDCK_CP/TDSPCKD_CP
C input to P register CLK
1.30
–0.13
1.42
–0.13
1.70
–0.13
ns
TDSPDCK_{PCINP, CRYCINP, MULTSIGNINP}/
TDSPCKD_{PCINP, CRYCINP, MULTSIGNINP}
{PCIN, CARRYCASCIN, MULTSIGNIN}
input to P register CLK
1.06
0.11
1.17
0.11
1.31
0.11
ns
Setup and Hold Times of the CE Pins
TDSPCCK_{CEA1A, CEA2A, CEB1B, CEB2B}/
TDSPCKC_{CEA1A, CEA2A, CEB1A, CEB2B}
{CEA1, CEA2A, CEB1B, CEB2B} input
to {A, B} register CLK
0.24
0.21
0.28
0.25
0.33
0.31
ns
TDSPCCK_CECC/TDSPCKC_CECC
CEC input to C register CLK
0.19
0.17
0.21
0.26
0.28
ns
Table 68: Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol
Description
Speed Grade
Units
-3
-2
-1
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