參數(shù)資料
型號: HW-V5-ML561-UNI-G-J
廠商: Xilinx Inc
文件頁數(shù): 33/91頁
文件大?。?/td> 0K
描述: EVALUATION PLATFORM VIRTEX-5
產(chǎn)品變化通告: Development Systems Discontinuation 16/Jan/2012
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 LXT
類型: FPGA
適用于相關(guān)產(chǎn)品: XC5VLX50T-FFG1136
所含物品: 評估平臺,線纜,CD,小型閃存卡,DDR2 DIMM,- 不包括電源 -
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
39
HSTL, Class IV
HSTL_IV
25
0
0.9
1.5
HSTL, Class I, 1.8V
HSTL_I_18
50
0
VREF
0.9
HSTL, Class II, 1.8V
HSTL_II_18
25
0
VREF
0.9
HSTL, Class III, 1.8V
HSTL_III_18
50
0
1.1
1.8
HSTL, Class IV, 1.8V
HSTL_IV_18
25
0
1.1
1.8
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL18_I
50
0
VREF
0.9
SSTL, Class II, 1.8V
SSTL18_II
25
0
VREF
0.9
SSTL, Class I, 2.5V
SSTL2_I
50
0
VREF
1.25
SSTL, Class II, 2.5V
SSTL2_II
25
0
VREF
1.25
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDS_25
100
0
0(4)
1.2
LVDSEXT (LVDS Extended Mode), 2.5V
LVDS_25
100
0
0(4)
1.2
BLVDS (Bus LVDS), 2.5V
BLVDS_25
100
0
0(4)
0
LDT (HyperTransport), 2.5V
LDT_25
100
0
0(4)
0.6
LVPECL (Low-Voltage Positive Emitter-Coupled Logic),
2.5V
LVPECL_25
100
0
0(4)
0
LVDCI/HSLVDCI
(Low-Voltage Digitally Controlled Impedance), 3.3V
LVDCI_33, HSLVDCI_33
1M
0
1.65
0
LVDCI/HSLVDCI, 2.5V
LVDCI_25, HSLVDCI_25
1M
0
1.25
0
LVDCI/HSLVDCI, 1.8V
LVDCI_18, HSLVDCI_18
1M
0
0.9
0
LVDCI/HSLVDCI, 1.5V
LVDCI_15, HSLVDCI_15
1M
0
0.75
0
HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL_I_DCI, HSTL_II_DCI
50
0
VREF
0.75
HSTL, Class III & IV, with DCI
HSTL_III_DCI, HSTL_IV_DCI
50
0
0.9
1.5
HSTL, Class I & II, 1.8V, with DCI
HSTL_I_DCI_18, HSTL_II_DCI_18
50
0
VREF
0.9
HSTL, Class III & IV, 1.8V, with DCI
HSTL_III_DCI_18,
HSTL_IV_DCI_18
50
0
1.1
1.8
SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL18_I_DCI, SSTL18_II_DCI
50
0
VREF
0.9
SSTL, Class I & II, 2.5V, with DCI
SSTL2_I_DCI, SSTL2_II_DCI
50
0
VREF
1.25
GTL (Gunning Transceiver Logic) with DCI
GTL_DCI
50
0
0.8
1.2
GTL Plus with DCI
GTLP_DCI
50
0
1.0
1.5
Notes:
1.
CREF is the capacitance of the probe, nominally 0 pF.
2.
Per PCI specifications.
3.
Per PCI-X specifications.
4.
The value given is the differential input voltage.
Table 59: Output Delay Measurement Methodology (Cont’d)
Description
I/O Standard
Attribute
RREF
(
Ω)
CREF(1)
(pF)
VMEAS
(V)
VREF
(V)
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