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參數(shù)資料
型號(hào)： HW-V5-ML561-UNI-G-J
廠商： Xilinx Inc
文件頁數(shù)： 20/91頁
文件大?。?/td> 0K
描述： EVALUATION PLATFORM VIRTEX-5
產(chǎn)品變化通告： Development Systems Discontinuation 16/Jan/2012
標(biāo)準(zhǔn)包裝： 1
系列： Virtex®-5 LXT
類型： FPGA
適用于相關(guān)產(chǎn)品： XC5VLX50T-FFG1136
所含物品： 評(píng)估平臺(tái)，線纜，CD，小型閃存卡，DDR2 DIMM，- 不包括電源 -
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
27
External Reference Inputs(4)
Positive Reference Input
Voltage Range
VREFP
Measured Relative to VREFN
2.45
2.5
2.55
Volts
Negative Reference Input
Voltage Range
VREFN
Measured Relative to AGND
–50
0
100
mV
Input current
IREF
ADCCLK
= 5.2 MHz
100
A
Power Requirements
Analog Power Supply
AVDD
Measured Relative to AVSS
2.45
2.5
2.55
Volts
Analog Supply Current
AIDD
ADCCLK
= 5.2 MHz
5
13
mA
Notes:
1.
Offset and gain errors are removed by enabling the System Monitor automatic gain calibration feature. See UG192: Virtex-5 FPGA System
Monitor User Guide.
2.
See "System Monitor Timing" in UG192: Virtex-5 FPGA System Monitor User Guide.
3.
See "Analog Inputs" in UG192: Virtex-5 FPGA System Monitor User Guide for a detailed description.
4.
Any variation in the reference voltage from the nominal VREFP = 2.5V and VREFN = 0V will result is a deviation from the ideal transfer
function.This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external
ratiometric type applications allowing the supply voltage and reference to vary by ±2% is permitted.
Table 51: Analog-to-Digital Specifications (Cont’d)
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
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