HT23B60
Rev. 1.10
24
March 1, 2004
Register
Label
Bits
R/W
Function
RTC
(24H)
6,4
~0
RO
Unused bit, read as 0
RTCEN
5
RW
Enable/disable the RTC counting (0: disable; 1: enable)
RTCSET
7
RW
RTC time-out flag (1: active; 0: inactive)
RTC & WDT & LCD Clock
RTC function
The real time clock (RTC) is used to supply a regular in-
ternal interrupt. Its time-out period is 2Hz. If the RTC
time-out occurs, the interrupt request flag RTCF and the
RTCSET flag will be set to 1. The interrupt vector for the
RTC is 14H. When the interrupt subroutine is serviced,
the interrupt request flag (RTCF) will be cleared to 0, but
the flag RTCSET maintain its original value. If RTC is
time-out, the flag RTCSET and RTCF will be set to 1.
The flag RTCSET can be cleared to 0 by software.
Input/Output Ports
There are 14 bidirectional input/output lines in the
HT23B60, labeled PAand PB, which are mapped to the
data memory of [12H], [14H], respectively. All these I/O
ports can be used for input and output operations. For
input operation, these ports are non-latching, that is, the
inputs must be ready at the T2 rising edge of instruction
MOV A,[m] (m=12H, 14H). For output operation, all data
is latched and remains unchanged until the output latch
is rewritten. Each I/O line has its own control register
(PAC, PBC) to control the input/output configuration.
With this control register, CMOS output or Schmitt trig-
ger input with or without pull-high resistor (software op-
tion 35H, 36H) structures can be reconfigured
dynamically under software control. To function as an
input, the corresponding latch of the control register
must be written a 1 . The pull-high resistance will ex-
hibit automatically if the pull-high option is selected. The
input source also depends on the control register. If the
control register bit is 1 , the input will read the pad
state. If the control register bit is 0 , the contents of the
latches will move to the internal bus. The latter is possi-
ble in read-modify-write instruction. For output func-
tion, CMOS is the only configuration. These control
registers are mapped to locations 13H, 15H. After a chip
reset, these input/output lines remain at high levels or
floating (mask option). Each bit of these input/output
latches can be set or cleared by the SET [m].i or CLR
[m].i (m=12H, 14H) instruction. Some instructions first
input data and then follow the output operations. For ex-
ample, the
SET [m].i ,
CLR [m].i ,
CPL [m]
and
CPLA [m] instructions read the entire port states into
the
CPU,
execute
the
(bit-operation), and then write the results back to the
latches or the accumulator. Each line of port A has the
capability to wake-up the device. Port B are share pad,
each pin function are defined by mask option, when the
PB3 be used as a normal I/O port, INT function must be
defined
operations
disable. (Set [0BH].4 to 0 ). The PB2, PB1 and PB0
share with serial data input, serial data output and serial
clock. If the serial function is selected, the related I/O
register (PB) cannot be used as general purpose regis-
ter.Readingtheregisterwillresulttoanunknownstate.
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