HT23B60
Rev. 1.10
22
March 1, 2004
Timer 0
The timer 0 contains 16-bit programmable count-up
counters and the clock source come from the system
clock divided by 4.
There are three registers related to the timer counter 0;
TMR0H (0CH), TMR0L (0DH), TMR0C(0EH). Writing
TMR0L only writes the data into a low byte buffer, and
writing TMR0H will simultaneously write the data and
the contents of the low byte buffer into the timer 0
preload register (16-bit). The Timer 0 preload register is
changed by writing TMR0H operations and writing
TMR0L will keep the Timer 0 preload register un-
changed.
Reading TMR0H will also latch the TMR0L into the low
byte buffer to avoid any false timing problem. Reading
TMR0Lreturnsthecontentsofthelowbytebuffer.Inthis
case, the low byte of the timer counter 0 cannot be read
directly. It must read the TMR0H first to make the low
byte contents of the Timer 0 be latched into the buffer.
The TMR0C is the Timer 0 control register, which de-
fines the Timer 0 options. The timer counter control reg-
isters define the operating mode, counting enable or
disable and active edge.
If the timer counter starts counting, it will count from the
current contents in the timer counter to FFFFH. Once an
overflow occurs, the counter is reloaded from the timer
counter preload register and at the same time generates
the corresponding interrupt request flag (T0F; bit of the
INTC0).
To enable the counting operation, the Timer ON bit
(TON; bit 4 of the TMR0C) should be set to 1. The over-
flow of the timer counter is one of the wake-up sources.
No matter what the operation mode is, writing a 0 to
ET0I can disable the corresponding interrupt service.
In the case of timer counter OFF condition, writing data
to the timer counter preload register will also reload that
data to the timer counter. But if the timer counter is
turned on, data written to the timer counter will only be
kept in the timer counter preload register. The timer
counter will still operate until overflow occurs.
When the timer counter (reading TMR0H) is read, the
clock will be blocked to avoid errors. As this may result
in a counting error, this must be taken into consideration
by the programmer.
Timer 2
The Timer 2 contains 16-bit programmable count-up
counters whose clock may come from the 32768 Hz os-
cillator or the clock source come from the system clock
divided by 4.
There are three registers related to the timer counter 2;
TMR2H (2AH), TMR2L (2BH), TMR2C(2CH). Writing
TMR2L only writes the data into a low byte buffer, and
writing TMR2H will simultaneously write the data and
the contents of the low byte buffer into the timer 2
preload register (16-bit). The timer 2 preload register is
changed by writing TMR2H operations and writing
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Register
Label
Bits
R/W
Function
TMR0C
(0EH)
0~2
RO
Unused bit, read as 0
3
Unused bit, read as 0
TON
4
RW
Enable/disable the timer counting (0=disabled; 1=enabled)
5
Unused bit, read as 0
TM0
TM1
6
7
RW
Fixed bit 7, 6=10, internal timer mode
Register
Label
Bits
R/W
Function
TMR2C
(2AH)
0~3
Unused bit, read as 0
TON
4
RW
Enable/disable the timer counting (0=disabled; 1=enabled)
5
Unused bit, read as 0
TM0
TM1
6
7
RW
Fixed bit 7, 6=10, internal timer mode