
HT23B60
Rev. 1.10
15
March 1, 2004
Indirect Addressing Register
Locations 00H and 02H are indirect addressing regis-
ters that are not physically implemented. Any read/write
operation of [00H] and [02H] access data memory
pointed to by MP0 (01H) and MP1 (03H) respectively.
Reading location 00H or 02H indirectly returns the result
00H, while writing to it results in no operation.
The data movement function between two indirect ad-
dressing registers is not supported. The memory pointer
registers MP0 and MP1, are 8-bit registers used to ac-
cess the data memory by combining corresponding indi-
rect addressing registers, Bank1~Bank11 and Bank15
can use MP1 only.
Accumulator
The accumulator is closely related to ALU operations. It
is mapped to location 05H of the data memory and can
also operate with immediate data. The data movement
between two data memory must pass through the accu-
mulator.
Arithmetic and Logic Unit
ALU
This circuit performs 8-bit arithmetic and logic operation.
The ALU provides the following functions:
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but
can also change the status register.
Status Register
STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF) and Watchdog time-out flag
(TO). It also records the status information and controls the
operation sequence.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like any
other register. Any data written into the status register
will not change the TO or PDF flags. In addition, opera-
tions related to the status register may give different re-
sults from those intended. The TO and PDF flags can
only be changed by a system power up, Watchdog
Timer overflow, executing the HALT instruction and
clearing the Watchdog Timer.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or exe-
cuting the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status register are important and the subroutine can
corrupt the status register, the programmer must take
precautions to save it properly.
Interrupt
The HT23B60 provides external and a D/Ainterrupt and
internal timer counter interrupts. The interrupt control
register (INTC;0BH, INTCH;1EH) contains the interrupt
control bits to set the enable/disable and the interrupt re-
quest flags.
Once an interrupt subroutine is serviced, all other inter-
rupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain interrupt
needsservicingwithintheserviceroutine,theEMIbitand
the corresponding INTC bit may be set to allow interrupt
nesting. If the stack is full, the interrupt request will not be
acknowledged, even if the related interrupt is enabled, un-
til the SP is decremented. If immediate service is desired,
the stack must be prevented from becoming full.
All these kinds of interrupt have a wake-up capability. As
an interrupt is serviced, a control transfer occurs by
pushing the program counter and A14~A13 bits onto the
Register
Labels
Bits
Function
STATUS
(0AH)
C
0
C is set if an operation results in a carry during an addition operation or if a borrow
does not take place during a subtraction operation; otherwise C is cleared. It is also
affected by a rotate through carry instruction.
AC
1
AC is set if an operation results in a carry out of the low nibbles in addition or no bor-
rowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.
Z
2
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is
cleared.
OV
3
OV is set if an operation results in a carry into the highest-order bit but not a carry
out of the highest-order bit, or vice versa; otherwise OV is cleared.
PDF
4
PDF is cleared by either a system power-up or executing the CLR WDT instruc-
tion. PDF is set by executing the HALT instruction.
TO
5
TO is cleared by a system power-up or executing the CLR WDT or HALT in-
struction. TO is set by a WDT time-out.
6,7
Unused bit, read as 0