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參數(shù)資料
| 型號： | HPLL-8001 |
| 英文描述： | PLL Frequency Synthesizer(鎖相環(huán)頻率合成器) |
| 中文描述： | 鎖相環(huán)頻率合成器（鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 77K |
| 代理商： | HPLL-8001 |
9
Status Registers
1
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B1 is the first bit which is transferred to the HPLL-8001.
B7 and B8:
Anti Backlash Pulse Width
B8
B7
0
0
0
1
1
0
1
1
Typical
10
6
4
2
Unit
ns
ns
ns
ns
B5 and B6:
B5
B6
Modes
Standby 2
0
0
1
Standby 1
0
1
0
Standby mode 1: All functions
powered down
Standby mode 2: Counters, charge pump,
and outputs are off. Only preamplifiers
stay active
Normal operation: All functions are active
1
1
B4:
B2
0
1
PD Polarity
negative
positive
positive means increasing VCO
frequency with increasing voltage
B2 and B3:
B2
0
0
1
1
B3
0
1
0
1
PO1
PO2
Modes
Test Modes
External Charge Pump, Mode 1
External Charge Pump, Mode 2
Internal Charge Pump mode
F
RN
φ
V
φ
VN
F
VN
φ
RN
φ
RN
I
REF
PROBIT
B1:
B1
0
1
Counter loading
asynchronous counter load
synchronous counter load
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