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參數(shù)資料
| 型號： | HPLL-8001 |
| 英文描述： | PLL Frequency Synthesizer(鎖相環(huán)頻率合成器) |
| 中文描述： | 鎖相環(huán)頻率合成器（鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 77K |
| 代理商： | HPLL-8001 |
8
Programmable Reference Divider (R Counter Register)
1
1
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
Note:
R16 is the MSB of the R counter value. R16 is the first bit which is transferred to the HPLL-8001.
Programmable Dividers (N and A Counter Registers)
Dual Mode
0
1
N1
N2
N3 ..........
N12
N13
N14
A1
A2
A3
A4
A5
A6
A7
Single Mode
0
1
N1
N2
N3
N4
N5
N6
N7
N8
N10
N11
N12
N13
N14
Note:
N14 is the MSB of the N counter value. A7 is the MSB of the A counter value. A7 is the first bit which is transferred
to the HPLL-8001.
HPLL-8001 Pin Description Table,
continued
No.
Mnemonic
Description
Typical Signal
12
PO1
Programmable output
Multifunction Output for the signals F
RN
,
φ
V
,
φ
VN
and
PROBIT (F
RN
,
φ
V
are the inverted signals of F
R
,
φ
VN
).
13
PO2
Programmable I/O
For the output signals F
VN
,
φ
RN
and the input signal I
REF
- The signals
φ
R
and
φ
V
are the digital output signals of the
phase and frequency detector for use with external active
current sources.
- The signals F
RN
and F
VN
are the scaled down signals of the
reference frequency and VCO-frequencies.
- The programmed bit PROBIT is assigned to PO1 output in
the internal charge pump mode. The standby mode does not
affect this function.
- In the internal charge pump mode the input signal I
REF
determines the value of the PD-output current.
14
LD
Lock detect
Unipolar output of the phase detector in the form of a pulse-
width modulated signal. The LD-pulse width corresponds
to the phase difference. In the locked state the LD-signal is at
H-level. In standby mode the output is resistive.
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