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參數(shù)資料
| 型號： | HM65W8512 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4 M PSRAM (512-kword ×8-bit)(4 M PSRAM (512k字 ×8位)) |
| 中文描述： | 4個(gè)M移動(dòng)存儲(chǔ)芯片（512 KWord的× 8位）（4個(gè)M移動(dòng)存儲(chǔ)芯片（為512k字× 8位）） |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 160K |
| 代理商： | HM65W8512 |
HM65W8512 Series
6
WE
: Write Enable (Input)
RAM is in write mode when
WE
is low, and is in read mode when
WE
is high. I/O data is fetched into
RAM by the rising edge of
WE
or
CE
(earlier timing) and the data is written into memory cells.
Refresh
There are three refresh modes : address refresh, automatic refresh and self refresh.
(1) Address refresh: Data is refreshed by accessing all 2048 row addresses every 32 ms. A read is one
method of accessing those addresses. Each row address (2048 addresses of A0 to A10) must be read at
least once every 32 ms. In address refresh mode,
OE
/
RFSH
can remain high. In this case, the I/O pins
remain at high impedance, but the refresh is done within RAM.
(2) Automatic refresh: Instead of address refresh, automatic refresh can be used. RAM goes to automatic
refresh mode if
OE
/
RFSH
falls while
CE
is high and it remains low for at least t
FAP
. One automatic
refresh cycle is executed by one low pulse of
OE
/
RFSH
. It is not necessary to input the refresh
address from outside since it is generated internally by an on-chip address counter. 2048 automatic
refresh cycles must be done every 32 ms.
(3) Self refresh: Self refresh mode is suitable for data retention by battery. In standby mode, a self refresh
starts automatically when
OE
/
RFSH
stays low for more than 8
μ
s. Refresh addresses are automatically
specified by the on-chip address counter, and the refresh period is determined by the on-chip timer.
Automatic refresh and self refresh are distinguished from each other by the width of the
OE
/
RFSH
low
pulse in standby mode. If the
OE
/
RFSH
low pulse is wider than 8
μ
s, RAM becomes into self refresh
mode; if the
OE
/
RFSH
low pulse is less than 8
μ
s, it is recognized as an automatic refresh instruction.
At the end of self refresh, refresh reset time (t
RFS
) is required to reset the internal self refresh operation of
the RAM. During t
,
CE
and
OE
/
RFSH
must be kept high. If auto refresh follows self refresh, low
transition of
OE
/
RFSH
at the beginning of automatic refresh must not occur during t
RFS
period.
Notes on Using the HM65W8512
Since pseudo static RAM consists of dynamic circuits like DRAM, its clock pins are more noise-sensitive
than conventional SRAM’s.
(1) If a short
CE
pulse of a width less than t
CE
min is applied to RAM, an incomplete read occurs and
stored data may be destroyed. Make sure that
CE
low pulses of less than t
CE
min are inhibited. Note
that a 10 ns
CE
low pulse may sometimes occur owing to the gate delay on the board if the
CE
signal is
generated by the decoding of higher address signals on the board. Avoid these short pulses.
(2)
OE
/
RFSH
works as refresh control in standby mode. A short
OE
/
RFSH
low pulse may cause an
incomplete refresh that will destroy data. Make sure that
OE
/
RFSH
low pulse of less than t
FAP
min are
also inhibited.
(3) t
OHC
and t
OCD
are the timing specs which distinguish the
OE
function of
OE
/
RFSH
from the
RFSH
function. The t
OHC
and t
OCD
specs must be strictly maintained.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| HM65W8512DFP-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Pseudo-Static RAM |
| HM65W8512DFP-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Pseudo-Static RAM |
| HM65W8512DRR-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Pseudo-Static RAM |
| HM65W8512DRR-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Pseudo-Static RAM |
| HM65W8512DTT-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Pseudo-Static RAM |
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