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參數(shù)資料
| 型號： | HCMOS |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Small Signal Bipolar Transistor; Collector Emitter Voltage, Vceo:100V; Transistor Polarity:N Channel; C-E Breakdown Voltage:100V; DC Current Gain Min (hfe):30; Package/Case:R245; Collector Base Voltage:120V |
| 中文描述： | HCMOS家庭特征 |
| 文件頁數(shù)： | 10/19頁 |
| 文件大?。?/td> | 87K |
| 代理商： | HCMOS |
March 1988
10
Philips Semiconductors
HCMOS family characteristics
FAMILY SPECIFICATIONS
HC TYPES
AC waveforms 74HC
AC waveforms 74HC
Fig.3 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.
handbook, halfpage
MGK564
10%
90%
90%
50%
50%
10%
INPUT
OUTPUT
tr
tf
tPHL
tTHL
tPLH
tTLH
GND
VCC
handbook, full pagewidth
MGK569
10 %
90%
50%
CLOCK
INPUT
VCC
GND
50%
DATA
INPUT
VCC
GND
10%
tPLH
90%
50%
OUTPUT
tsu
tPHL
tsu
tTLH
tTHL
50%
SET,
RESET,
PRESET
INPUT
VCC
GND
tr
tf
tWH
th
th
tWL
trem
1/fmax
Fig.4
Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for
sequential logic ICs.
(1) In Fig.4 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals (SET, RESET
and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual active levels of the forcing signals
are specified in the individual device data sheet.
(2) For AC measurements: t
r
= t
f
= 6 ns; when measuring f
max
, there is no constraint on t
r
, t
f
with 50% duty factor.
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