參數(shù)資料
型號(hào): GS8180S36
廠商: GSI TECHNOLOGY
英文描述: 512K x 36Bit Separate I/O Sigma DDR SRAM(512K x 36位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
中文描述: 為512k × 36Bit分離I / O西格瑪?shù)腄DR SRAM的(為512k × 36位獨(dú)立的I / O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
文件頁(yè)數(shù): 2/32頁(yè)
文件大?。?/td> 853K
代理商: GS8180S36
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2/32
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8180S09/18/36B-333/300/275/250
8180S36 Pinout
512K x 36 Separate I/O—Top View
1
2
3
4
5
6
7
8
9
10
11
A
Dc1
Dc2
A
E2
A
(16M)
MCL
A
(8M)
E3
A
Qb1
Qb2
B
Dc3
Dc4
MCL
NC
A
W
A
MCL
NC
Qb3
Qb4
C
Dc5
Dc6
NC
MCL
NC
(128M)
E1
NC
NC
MCL
Qb5
Qb6
D
Dc7
Dc8
V
SS
NC
NC
MCL
NC
NC
V
SS
Qb7
Qb8
E
Dc9
Qc1
V
DDQ
V
DDQ
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
Db1
Qb9
F
Qc3
Qc2
V
SS
V
SS
V
SS
ZQ
V
SS
V
SS
V
SS
Db2
Db3
G
Qc5
Qc4
V
DDQ
V
DDQ
V
DD
EP2
V
DD
V
DDQ
V
DDQ
Db4
Db5
H
Qc7
Qc6
V
SS
V
SS
V
SS
EP3
V
SS
V
SS
V
SS
Db6
Db7
J
Qc9
Qc8
V
DDQ
V
DDQ
V
DD
M4
V
DD
V
DDQ
V
DDQ
Db8
Db9
K
CQ2
CQ2
CK
NC
V
SS
MCL
V
SS
NC
NC
CQ1
CQ1
L
Dd9
Dd8
V
DDQ
V
DDQ
V
DD
M2
V
DD
V
DDQ
V
DDQ
Qa8
Qa9
M
Dd7
Dd6
V
SS
V
SS
V
SS
M3
V
SS
V
SS
V
SS
Qa6
Qa7
N
Dd5
Dd4
V
DDQ
V
DDQ
V
DD
MCH
V
DD
V
DDQ
V
DDQ
Qa4
Qa5
P
Dd3
Dd2
V
SS
V
SS
V
SS
MCL
V
SS
V
SS
V
SS
Qa2
Qa3
R
Qd9
Dd1
V
DDQ
V
DDQ
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
Qa1
Da9
T
Qd7
Qd8
V
SS
NC
NC
MCL
NC
NC
V
SS
Da8
Da7
U
Qd5
Qd6
NC
A
NC
(64M)
A
NC
(32M)
A
NC
Da6
Da5
V
Qd3
Qd4
A
(2M)
A
A
A1
A
A
A
(4M)
Da4
Da3
W
Qd1
Qd2
TMS
TDI
A
MCL
A
TDO
TCK
Da2
Da1
Rev 10
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch—MS-028vBC
Note:
Users of CMOS I/O Sigma RAMs may wish to connect D4, D8, T4, T8 and K4 to V
DDQ
/2 to allow alternate use of HSTL
I/O Sigma RAMs.
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