參數(shù)資料
型號: GPTRM
英文描述: General-Purpose Timer Reference Manual
中文描述: 通用定時器參考手冊
文件頁數(shù): 51/90頁
文件大?。?/td> 647K
代理商: GPTRM
GPT
REFERENCE MANUAL
INTERRUPTS
MOTOROLA
7-5
Figure 7-4 Timer Interrupt Flag Registers (TFLG1/TFLG2)
OCxF — Output Compare x Flag
This flag is set each time TCNT matches the value in output compare register x.
ICxF — Input Capture x Flag
This flag is set each time a selected edge is detected at the input capture x pin.
I4/O5F — Input Capture 4/Output Compare 5 Flag
If the I4/O5 pin is configured as input capture 4, this flag is set each time a selected
edge is detected at the I4/O5 pin. If the I4/O5 pin is configured as output compare 5,
this flag is set each time TCNT matches the value in output compare register 5.
TOF — Timer Overflow Flag
This flag is set each time TCNT advances from a value of $FFFF to $0000.
PAOVF — Pulse Accumulator Overflow Flag
This flag is set each time the pulse accumulator counter advances from a value of $FF
to $00.
PAIF — Pulse Accumulator Flag
In event counting mode, this bit is set when an active edge is detected on the PAI pin.
In gated time accumulation mode, this bit is set at the end of the timed period (when
going from the active (counting) state to the inactive (no longer counting) state).
7.1.3 Enabling Interrupts
Even though the interrupt level in the ICR register may be set to a level between one
and seven, the GPT will not generate an interrupt to the CPU unless the individual
channels have their respective interrupts enabled. However, the GPT can still operate
in polled mode, as described above.
Interrupts are enabled by setting the interrupt enable bits in timer interrupt mask reg-
ister (TMSK1–2). The bit indicating the occurrence of an event is set in the TFLG reg-
ister. This is the interrupt status flag. If the corresponding bit in the TMSK register is
set, the CPU will receive a hardware interrupt request.
Note that upon exit from an interrupt service routine, the corresponding interrupt status
flag must be cleared. If not cleared, the same interrupt will be pending, and the CPU
will respond as if a new interrupt occurred.
TFLG1/TFLG2 —
Timer Interrupt Flag Registers 1–2
$YFF922
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I4/O5F
OC4F
OC3F
OC2F
OC1F
IC3F
IC2F
IC1F
TOF
0
PAOVF
PAIF
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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