參數(shù)資料
型號(hào)： GPTRM
英文描述： General-Purpose Timer Reference Manual
中文描述： 通用定時(shí)器參考手冊(cè)
文件頁(yè)數(shù)： 31/90頁(yè)
文件大?。?/td> 647K
代理商： GPTRM
GPT
REFERENCE MANUAL
COMPARE/CAPTURE UNIT
MOTOROLA
3-9
OC1Dx — OC1 Data Bits
0 =If OC1Mx is set, transfer zero to the corresponding parallel data port bit on OC1
match.
1 =If OC1Mx is set, transfer one to the corresponding parallel data port bit on OC1
match.
An interrupt can also be generated on a successful output compare if the correspond-
ing interrupt enable bit (OCxI) is set in TMSK1.
If not needed by the output compare one function, the OC1 pin can be used to output
the clock selected as the input to the timer counter register (TCNT). Note that this clock
does not have a 50% duty cycle. For more details on this feature, refer to the functional
description of the prescaler in
5.1 Prescaler
.
3.3.4 Timer Compare Force Register (CFORC)
The CFORC register (
Figure 3-9
) allows forced early compares. FOC[5:1] correspond
to the five output compares. These bits are set for each output compare that is to be
forced. The action taken as a result of a forced compare is the same as if there was a
match between the OCx register and the free-running counter, except that the corre-
sponding interrupt status flag bits are not set. The forced channels will trigger their pro-
grammed pin actions to occur immediately after the write to CFORC.
The CFORC register is implemented as the upper byte of a 16-bit register which also
contains the PWM control register (PWMC). It can be accessed as eight bits or a word
access can be used. Reads of the force compare bits (FOCx) have no meaning and
always return zeros. These bits are self negating.
The CFORC bits should not be used on an output compare function that is pro-
grammed to toggle its output on a successful compare, because a normal compare
occurring immediately before or after the force may result in undesirable operation.
* These bits are part of PWMC.
Refer to the
SECTION 6 PULSE-WIDTH MODULATION UNIT
for information on FPWMA and FPWMB.
NOTE: The address shown is on a word boundary; however, the register can be accessed by a word or byte cycle.
Figure 3-9 Timer Compare Register (CFORC)
FOCx — Force Output Compare Bits
0 = Has no meaning
1 = Causes pin action programmed for OCx, except that the OCxF flag is not set
CFORC —
Compare Force Register
$YFF924
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FOC5
FOC4
FOC3
FOC2
FOC1
0
FPWMAT
FPWMB
*
*
*
*
*
*
*
*
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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