參數(shù)資料
型號(hào): GPTRM
英文描述: General-Purpose Timer Reference Manual
中文描述: 通用定時(shí)器參考手冊
文件頁數(shù): 49/90頁
文件大?。?/td> 647K
代理商: GPTRM
GPT
REFERENCE MANUAL
INTERRUPTS
MOTOROLA
7-3
The priority adjust bits (PAB) in the interrupt configuration register (ICR) can change
the priority of one of the channels. The user can place any single interrupt source at
the highest priority level by changing the PAB value. Other than this one exception, all
other priority relationships remain the same.
Table 7-1
shows the priority relationships
of the timer channels.
X = 4-bit vector base address (VBA)
7.1.1 GPT Interrupt Configuration Register (ICR)
The ICR controls the interrupt operation of the GPT.
Figure 7-3 GPT Interrupt Configuration Register (ICR)
PAB — Priority Adjust Bits
The GPT has 11 sources capable of generating an interrupt. These bits specify the sin-
gle interrupt source that has the highest priority level. All of the other interrupt sources
maintain their relative priority.
For example, a $4 written to PAB will make OC1 the highest priority channel. When
OC1 generates an interrupt, the low nibble of the vector will be $0. The remaining
channels maintain their original relative priority and vector addresses.
Table 7-1 Timer Interrupt Priorities and Vector Number
Interrupt Source
Priority Level
Vector Number
Name
IC1
IC2
IC3
OC1
OC2
OC3
OC4
IC4/OC5
TOF
PAOVF
PAIF
Function
Adjusted Channel
Input Capture 1
Input Capture 2
Input Capture 3
Output Compare 1
Output Compare 2
Output Compare 3
Output Compare 4
Input Capture 4/Output Compare 5
Timer Overflow Flag
Pulse Accumulator Overflow Flag
Pulse Accumulator Input Flag
0 (Highest)
1
2
3
4
5
6
7
8
9
10
11 (Lowest)
$X0
$X1
$X2
$X3
$X4
$X5
$X6
$X7
$X8
$X9
$XA
$XB
ICR —
Interrupt Configuration Register
$YFF904
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PAB
0
IRL
VBA
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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