- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383009 > GM5110-H (Electronic Theatre Controls, Inc.) XGA/SXGA LCD Controller PDF資料下載
參數(shù)資料
| 型號： | GM5110-H |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | XGA/SXGA LCD Controller |
| 中文描述： | 的XGA / SXGA LCD控制器 |
| 文件頁數(shù)： | 45/51頁 |
| 文件大小： | 1379K |
| 代理商： | GM5110-H |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁當(dāng)前第45頁第46頁第47頁第48頁第49頁第50頁第51頁
***
Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
June 2002
38
C5110-DAT-01C
A 2-wire data transfer consists of a stream of serially transmitted bytes formatted as shown in
the figure below. A transfer is initiated (START) by a high-to-low transition on HFSn while
HCLK is held high. A transfer is terminated by a STOP (a low-to-high transition on HFSn
while HCLK is held high) or by a START (to begin another transfer). The HFSn signal must
be stable when HCLK is high, it may only change when HCLK is low (to avoid being
misinterpreted as START or STOP).
ADDRESS BYTE
HFSn
1
2
3
7
8
9
HCLK
4
5
6
1
2
8
9
DATA BYTE
ACK
ACK
START
STOP
Receiver acknowledges by holding SDA low
R/W
A6
A1
A2
A3
A4
A5
A0
D6
D7
D0
Figure 27.
2-Wire Protocol Data Transfer
Each transaction on the HFSn is in integer multiples of 8 bits (i.e. bytes). The number of
bytes that can be transmitted per transfer is unrestricted. Each byte is transmitted with the
most significant bit (MSB) first. After the eight data bits, the master releases the HFSn line
and the receiver asserts the HFSn line low to acknowledge receipt of the data. The master
device generates the HCLK pulse during the acknowledge cycle. The addressed receiver is
obliged to acknowledge each byte that has been received.
The Write Address Increment and the Write Address No Increment operations allow one or
multiple registers to be programmed with only sending one start address. In Write Address
Increment, the address pointer is automatically incremented after each byte has been sent and
written. The transmission data stream for this mode is illustrated in Figure 28 below. The
highlighted sections of the waveform represent moments when the transmitting device must
release the HFSn line and wait for an acknowledgement from the gm5110/20 (the slave
receiver).
ACK
ACK
ACK
OPERATION CODE
START
HFSn
HCLK
STOP
DEVICE ADDRESS
REGISTER ADDRESS
DATA
DATA
R/W
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
9
A8
Two MSBs of register address
A9
Figure 28.
2-Wire Write Operations (0x1x and 0x2x)
The Read Address Increment (0x90) and Read Address No Increment (0xA0) operations are
illustrated in Figure 29. The highlighted sections of the waveform represent moments when
the transmitting device must release the HFSn line and waits for an acknowledgement from
the master receiver.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GM5120 | XGA/SXGA LCD Controller |
| GM5120-H | XGA/SXGA LCD Controller |
| GM2126 | ANALOG INTERFACE ONPANEL SXGA LCD CONTROLLER WITH RSDS TRANSMITTER |
| GM5115 | ONPANEL LCD PANEL CONTROLLER |
| GM5115-H | ONPANEL LCD PANEL CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GM5115 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ONPANEL LCD PANEL CONTROLLER |
| GM5115-H | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ONPANEL LCD PANEL CONTROLLER |
| GM5120 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:XGA/SXGA LCD Controller |
| GM5120-H | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:XGA/SXGA LCD Controller |
| GM5125 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ONPANEL LCD PANEL CONTROLLER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。