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參數(shù)資料
| 型號： | GM5110-H |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | XGA/SXGA LCD Controller |
| 中文描述： | 的XGA / SXGA LCD控制器 |
| 文件頁數(shù)： | 27/51頁 |
| 文件大?。?/td> | 1379K |
| 代理商： | GM5110-H |
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***
Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
June 2002
20
C5110-DAT-01C
For ADC interlaced inputs, the gm5110/20 may be programmed to automatically determine
the field type (even or odd) from the VSYNC/HSYNC relative timing. See Input Format
Measurement, Section 4.5.
4
4
.
.
4
4
D
D
V
V
I
I
R
R
e
e
c
c
e
e
i
i
v
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r
B
B
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The Ultra-Reliable DVI
TM
receiver block of the gm5110/20 is compliant with DVI1.0 single
link specifications. Digital Visual Interface (DVI) is a standard that uses Transition
Minimized Differential Signaling protocol (TMDS). This block supports an input clock
frequency ranging from 20 MHz to 165 MHz.
4.4.1 DVI Receiver Characteristics
Table 16 summarizes the characteristics of the four Receiver Pair inputs. Please note that it is
very important to follow the recommended layout guidelines for these signals. These are
described in "gm5115 Layout Guidelines" document number C5115-SLG-01A.
Table 16. DVI Receiver Characteristics
MIN
TYP
MAX
NOTE
DC Characteristics
Differential Input Voltage
Input Common Mode Voltage
150mV
AVDD
–300m V
AVDD
-10mV
AC Characteristics
20 MHz
150mV
1200mV
AVDD
-37mV
AVDD
+10mV
Behavior when Transmitter Disable
Input clock frequency
Input differential sensitivity (Peak-to-peak)
Max differential input (peak-to-peak)
Allowable Intra-Pair skew at Receiver
Allowable Inter-Pair skew at Receiver
Worst case differential input clock jitter
tolerance
165 MHz
1560 mV
250 ps
4.0 ns
188 ps
Input clock = 160 MHz
Through register programming, the receiver unit may be placed in one of three states:
Active:
The receiver block is fully on and running.
Standby:
Only the RC (clock) channel remains active. Data and other control signals are
not decoded.
Off:
The receiver block is powered down.
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