- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17112 > EVAL-ADUC7028QSZ (Analog Devices Inc)KIT DEV ADUC7028 QUICK START PDF資料下載
參數(shù)資料
| 型號： | EVAL-ADUC7028QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 99/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV ADUC7028 QUICK START |
| 產品培訓模塊： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters Process Control |
| 標準包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類型： | MCU |
| 適用于相關產品： | ADuC7028 |
| 所含物品： | 評估板、電源、纜線、軟件和說明文檔 |
| 產品目錄頁面： | 739 (CN2011-ZH PDF) |
| 相關產品： | ADUC7028BBCZ62-RL-ND - IC MCU FLASH 62K 12BIT ADUC7028BBCZ62-ND - IC MCU FLASH 62K 12BIT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁當前第99頁第100頁第101頁第102頁第103頁第104頁
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Rev. F | Page 94 of 104
GROUNDING AND BOARD LAYOUT
RECOMMENDATIONS
As with all high resolution data converters, special attention
must be paid to grounding and PC board layout of the
ADuC7019/20/21/22/24/25/26/27/28/29-based designs to
achieve optimum performance from the ADCs and DAC.
Although the parts have separate pins for analog and digital
ground (AGND and IOGND), the user must not tie these to
two separate ground planes unless the two ground planes are
connected very close to the part. This is illustrated in the
simplified example shown in Figure 91a. In systems where
digital and analog ground planes are connected together
somewhere else (at the system power supply, for example), the
planes cannot be reconnected near the part because a ground
loop results. In these cases, tie all the ADuC7019/20/21/
22/24/25/26/27/28/29 AGND and IOGND pins to the analog
ground plane, as illustrated in Figure 91b. In systems with only
one ground plane, ensure that the digital and analog components
are physically separated onto separate halves of the board so
that digital return currents do not flow near analog circuitry
(and vice versa).
The ADuC7019/20/21/22/24/25/26/27/28/29 can then be
placed between the digital and analog sections, as illustrated in
04
95
5-
0
47
a.
PLACE ANALOG
COMPONENTS HERE
PLACE DIGITAL
COMPONENTS HERE
AGND
DGND
b.
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS HERE
AGND
DGND
c.
PLACE ANALOG
COMPONENTS HERE
PLACE DIGITAL
COMPONENTS HERE
DGND
Figure 91. System Grounding Schemes
In all of these scenarios, and in more complicated real-life
applications, the user should pay particular attention to the flow
of current from the supplies and back to ground. Make sure the
return paths for all currents are as close as possible to the paths
the currents took to reach their destinations.
For example, do not power components on the analog side (as
currents from IOVDD to flow through AGND. Avoid digital
currents flowing under analog circuitry, which can occur if a
noisy digital chip is placed on the left half of the board (shown
in Figure 91c). If possible, avoid large discontinuities in the
ground plane(s) such as those formed by a long trace on the same
layer because they force return signals to travel a longer path.
In addition, make all connections to the ground plane directly,
with little or no trace separating the pin from its via to ground.
When connecting fast logic signals (rise/fall time < 5 ns) to any of
the ADuC7019/20/21/22/24/25/26/27/28/29 digital inputs, add a
series resistor to each relevant line to keep rise and fall times
longer than 5 ns at the part’s input pins. A value of 100 Ω or
200 Ω is usually sufficient to prevent high speed signals from
coupling capacitively into the part and affecting the accuracy
of ADC conversions.
CLOCK OSCILLATOR
The clock source for the ADuC7019/20/21/22/24/25/26/27/28/29
can be generated by the internal PLL or by an external clock
input. To use the internal PLL, connect a 32.768 kHz parallel
resonant crystal between XCLKI and XCLKO, and connect a
capacitor from each pin to ground as shown in Figure 92. The
crystal allows the PLL to lock correctly to give a frequency of
41.78 MHz. If no external crystal is present, the internal
oscillator is used to give a typical frequency of 41.78 MHz ± 3%.
0
495
5-
048
ADuC7026
TO
INTERNAL
PLL
12pF
45
XCLKI
32.768kHz
12pF
44
XCLKO
Figure 92. External Parallel Resonant Crystal Connections
To use an external source clock input instead of the PLL (see
Figure 93), Bit 1 and Bit 0 of PLLCON must be modified.The
external clock uses P0.7 and XCLK.
0
495
5-
049
ADuC7026
TO
FREQUENCY
DIVIDER
XCLKO
XCLKI
XCLK
EXTERNAL
CLOCK
SOURCE
Figure 93. Connecting an External Clock Source
Using an external clock source, the ADuC7019/20/21/22/24/
25/26/27/28/29-specified operational clock speed range is
50 kHz to 44 MHz ± 1%, which ensures correct operation of
the analog peripherals and Flash/EE.
相關PDF資料 |
PDF描述 |
|---|---|
| GMM12DREN | CONN EDGECARD 24POS .156 EYELET |
| GSM12DREH | CONN EDGECARD 24POS .156 EYELET |
| EA-XPR-001 | BOARD LPCXPRESSO LPC1343 |
| EVAL-ADUC841QSZ | KIT DEV FOR ADUC841 QUICK START |
| HBM11DRAI | CONN EDGECARD 22POS R/A .156 SLD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADUC7029QSZ | 功能描述:EVAL DEV SYSTEM FOR ADUC7029 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:* 標準包裝:1 系列:PICDEM™ 類型:MCU 適用于相關產品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產品目錄頁面:659 (CN2011-ZH PDF) |
| EVAL-ADUC7029QSZ | 制造商:Analog Devices 功能描述:Silicon Manufacturer:Analog Devices C |
| EVAL-ADUC7032QSPZ | 制造商:Analog Devices 功能描述:EVAL BD FOR ADUC7032 - Bulk |
| EVAL-ADUC7033QSPZ | 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Bulk |
| EVAL-ADUC7034QSPZ | 制造商:Analog Devices 功能描述:EVALUATION BOARD - Boxed Product (Development Kits) |
發(fā)布緊急采購，3分鐘左右您將得到回復。