- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17112 > EVAL-ADUC7028QSZ (Analog Devices Inc)KIT DEV ADUC7028 QUICK START PDF資料下載
參數(shù)資料
| 型號： | EVAL-ADUC7028QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 98/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV ADUC7028 QUICK START |
| 產(chǎn)品培訓(xùn)模塊： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters Process Control |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC7028 |
| 所含物品： | 評估板、電源、纜線、軟件和說明文檔 |
| 產(chǎn)品目錄頁面： | 739 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | ADUC7028BBCZ62-RL-ND - IC MCU FLASH 62K 12BIT ADUC7028BBCZ62-ND - IC MCU FLASH 62K 12BIT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁當(dāng)前第98頁第99頁第100頁第101頁第102頁第103頁第104頁
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 93 of 104
HARDWARE DESIGN CONSIDERATIONS
POWER SUPPLIES
The ADuC7019/20/21/22/24/25/26/27/28/29 operational power
supply voltage range is 2.7 V to 3.6 V. Separate analog and
digital power supply pins (AVDD and IOVDD, respectively) allow
AVDD to be kept relatively free of noisy digital signals often
present on the system IOVDD line. In this mode, the part can
also operate with split supplies; that is, it can use different
voltage levels for each supply. For example, the system can
be designed to operate with an IOVDD voltage level of 3.3 V
whereas the AVDD level can be at 3 V or vice versa. A typical
split supply configuration is shown in Figure 87.
04955-
044
ADuC7026
0.1F
ANALOG
SUPPLY
10F
73
74
AVDD
75
DACVDD
8
GNDREF
70
DACGND
71
AGND
67
REFGND
26
IOVDD
54
25
IOGND
53
0.1F
+
–
DIGITAL
SUPPLY
10F
+
–
Figure 87. External Dual Supply Connections
As an alternative to providing two separate power supplies, the
user can reduce noise on AVDD by placing a small series resistor
and/or ferrite bead between AVDD and IOVDD and then decoupling
AVDD separately to ground. An example of this configuration is
shown in Figure 88. With this configuration, other analog circuitry
(such as op amps and voltage reference) can be powered from
the AVDD supply line as well.
04955-
045
ADuC7026
0.1F
BEAD
1.6
73
74
AVDD
75
DACVDD
8
GNDREF
70
DACGND
71
AGND
67
REFGND
26
IOVDD
54
25
IOGND
53
0.1F
DIGITAL SUPPLY
10F
+
–
Figure 88. External Single Supply Connections
Note that in both Figure 87 and Figure 88, a large value (10 F)
reservoir capacitor sits on IOVDD, and a separate 10 F capacitor
sits on AVDD. In addition, local small-value (0.1 F) capacitors are
located at each AVDD and IOVDD pin of the chip. As per standard
design practice, be sure to include all of these capacitors and ensure
that the smaller capacitors are close to each AVDD pin with trace
lengths as short as possible. Connect the ground terminal of
each of these capacitors directly to the underlying ground plane.
Finally, note that the analog and digital ground pins on the
ADuC7019/20/21/22/24/25/26/27/28/29 must be referenced to
the same system ground reference point at all times.
IOVDD Supply Sensitivity
The IOVDD supply is sensitive to high frequency noise because it
is the supply source for the internal oscillator and PLL circuits.
When the internal PLL loses lock, the clock source is removed
by a gating circuit from the CPU, and the ARM7TDMI core
stops executing code until the PLL regains lock. This feature
ensures that no flash interface timings or ARM7TDMI timings
are violated.
Typically, frequency noise greater than 50 kHz and 50 mV p-p
on top of the supply causes the core to stop working.
If decoupling values recommended in the Power Supplies
section do not sufficiently dampen all noise sources below
is recommended.
ADuC7026
26
IOVDD
54
25
IOGND
53
0.1F
DIGITAL
SUPPLY
10F
+
–
1H
04955-
087
Figure 89. Recommended IOVDD Supply Filter
Linear Voltage Regulator
Each ADuC7019/20/21/22/24/25/26/27/28/29 requires a single
3.3 V supply, but the core logic requires a 2.6 V supply. An on-
chip linear regulator generates the 2.6 V from IOVDD for the
core logic. The LVDD pin is the 2.6 V supply for the core logic.
An external compensation capacitor of 0.47 F must be
connected between LVDD and DGND (as close as possible to
these pins) to act as a tank of charge as shown in Figure 90.
04955-
046
ADuC7026
0.47
mF
27 LVDD
28 DGND
Figure 90. Voltage Regulator Connections
The LVDD pin should not be used for any other chip. It is also
recommended to use excellent power supply decoupling on
IOVDD to help improve line regulation performance of the on-
chip voltage regulator.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GMM12DREN | CONN EDGECARD 24POS .156 EYELET |
| GSM12DREH | CONN EDGECARD 24POS .156 EYELET |
| EA-XPR-001 | BOARD LPCXPRESSO LPC1343 |
| EVAL-ADUC841QSZ | KIT DEV FOR ADUC841 QUICK START |
| HBM11DRAI | CONN EDGECARD 22POS R/A .156 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADUC7029QSZ | 功能描述:EVAL DEV SYSTEM FOR ADUC7029 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:* 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF) |
| EVAL-ADUC7029QSZ | 制造商:Analog Devices 功能描述:Silicon Manufacturer:Analog Devices C |
| EVAL-ADUC7032QSPZ | 制造商:Analog Devices 功能描述:EVAL BD FOR ADUC7032 - Bulk |
| EVAL-ADUC7033QSPZ | 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Bulk |
| EVAL-ADUC7034QSPZ | 制造商:Analog Devices 功能描述:EVALUATION BOARD - Boxed Product (Development Kits) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。