參數(shù)資料
型號： EP20K60EQC208
廠商： ALTERA CORP
元件分類： PLD
英文描述： LOADABLE PLD, PQFP208
封裝： 30.40 X 30.40 MM, 0.50 MM PITCH, PLASTIC, QFP-208
文件頁數(shù)： 35/114頁
文件大?。?/td> 4116K
代理商： EP20K60EQC208
IGLOO nano DC and Switching Characteristics
Ad vance v0.2
2-13
Combinatorial Cells Contribution—PC-CELL
PC-CELL = NC-CELL*
α
1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-18 on
FCLK is the global clock signal frequency.
Routing Net Contribution—PNET
PNET = (NS-CELL + NC-CELL) *
α
1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-18 on
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution—PINPUTS
PINPUTS = NINPUTS *
α
2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
α
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-18 on page 2-14.
FCLK is the global clock signal frequency.
I/O Output Buffer Contribution—POUTPUTS
POUTPUTS = NOUTPUTS *
α
2 / 2 *
β
1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
α
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-18 on page 2-14.
β
1 is the I/O buffer enable rate—guidelines are provided in Table 2-19 on page 2-14.
FCLK is the global clock signal frequency.
RAM Contribution—PMEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK *
β
2 + PAC12 * NBLOCK * FWRITE-CLOCK *
β
3
NBLOCKS is the number of RAM blocks used in the design.
FREAD-CLOCK is the memory read clock frequency.
β
2 is the RAM enable rate for read operations.
FWRITE-CLOCK is the memory write clock frequency.
β
3 is the RAM enable rate for write operations—guidelines are provided in Table 2-19
PLL Contribution—PPLL
PPLL = PDC4 + PAC13 *FCLKOUT
FCLKOUT is the output clock frequency.
1
1.
If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its
corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K60EQC208-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 256 Macro 148 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K60EQC208-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60EQC208-1N 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 256 Macro 148 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K60EQC208-1X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 256 Macro 148 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K60EQC208-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 256 Macro 148 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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