參數(shù)資料
型號(hào)： EN29LV160B-90TIP
廠商： Eon Silicon Solution Inc.
英文描述： 16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only
中文描述： 16兆位（2048K × 8位/ 1024K x 16位）閃存引導(dǎo)扇區(qū)閃存，CMOS 3.0伏，只
文件頁(yè)數(shù)： 10/45頁(yè)
文件大小： 438K
代理商： EN29LV160B-90TIP
This Data Sheet may be revised by subsequent versions
2003 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
18
EN29LV160
Rev. A, Issue Date: 2004/03/30
status bits are required for sector and mode information. Refer to Table 5 to compare outputs for DQ2 and
DQ6.
Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm. See
also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing
diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.
Typically, a system would note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not
toggling, the device has completed the program or erase operation. The system can read array data on
DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped
toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully
completed the program or erase operation. If it is still toggling, the device did not complete the operation
successfully, and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read
cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to
perform other system tasks. In this case, the system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Flowchart 6).
Write Operation Status
Operation
DQ7
DQ6
DQ5
DQ3
DQ2
RY/BY
#
Embedded Program
Algorithm
DQ7#
Toggle
0
N/A
No
toggle
0
Standar
d Mode
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
0
Reading within Erase
Suspended Sector
1
No
Toggle
0
N/A
Toggle
1
Reading within Non-Erase
Suspended Sector
Data
1
Erase
Suspend
Mode
Erase-Suspend Program
DQ7#
Toggle
0
N/A
0
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